Xilinx LogiCORE IP v1.02a Product Manual page 17

Table 2-17: General Purpose Input x Register Bit Definitions
Bit(s)
31:C_GPIx_SIZE
[C_GPIx_SIZE-1]:0
Interrupt Status Register (IRQ_STATUS)
The Interrupt Status Register holds information on interrupt events that have occurred. The
register is read-only and the IRQ_ACK register should be used to clear individual interrupts.
Table 2-18: Interrupt Status Register (IRQ_STATUS)
Reserved
31 C_INTC_EXT_INTR+16 C_INTC_EXT_INTR+15
Table 2-19: Interrupt Status Register Bit Definitions
Bit(s)
31:[C_INTC_EXT_INTR + 16]
[C_INTC_EXT_INTR+15]:16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I/O Module v1.02a
PG052 October 16, 2012
Name Core Reset
Access Value
- R 0 Reserved
GPIx R 0 Register reads value input on the I/O Module GPIx port input
signals
INTC_Interrupt
Core
Name
Access
-
INTC_Interrupt
-
GPI4
GPI3
GPI2
GPI1
FIT4
FIT3
FIT2
FIT1
PIT4
PIT3
PIT2
PIT1
UART_RX
UART_TX
UART_ERR
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Description
Reserved
16 15
Reset
Value
Reserved
R 0
R 0 I/O Module external interrupt input signal
INTC_Interrupt [C_INTC_EXT_INTR-1:0]
mapped to corresponding bit positions in
IRQ_STATUS
R 0 Reserved
GPI4 changed
R 0
R 0 GPI3 changed
R 0 GPI2 changed
GPI1 changed
R 0
R 0 FIT4 strobe
R 0 FIT3 strobe
FIT2 strobe
R 0
R 0 FIT1 strobe
R 0 PIT4 lapsed
R 0 PIT3 lapsed
PIT2 lapsed
R 0
R 0 PIT1 lapsed
R 0 UART Received Data
R 0 UART Transmitted Data
UART Error
R 0
Register Space
Internal Interrupts
11 10
Description
Product Specification
0
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