Xilinx LogiCORE IP v1.02a Product Manual page 21

Interrupt Address Vector Registers (IRQ_VECTOR_0 -
IRQ_VECTOR_31)
These 32 registers are used as Interrupt Address Vector for the corresponding interrupt bit.
The content is sent to the processor on the INTC_Interrupt_Address port when the interrupt
occurs. The registers are write-only.
The two least significant bits and the most significant bits greater than or equal to
C_INTC_ADDR_WIDTH (if any) of each register are fixed to 0.
For reserved interrupt bits (11-15), and unused external interrupts (greater than
C_INTC_EXT_INTR+15), writing to the corresponding register has no effect.
The registers are only implemented when fast interrupt mode is enabled, by setting
C_INTC_HAS_FAST to 1.
Table 2-28: Interrupt Address Vector Register (IRQ_VECTOR_x)
0
31 C_INTC_ADDR_WIDTH C_INTC_ADDR_WIDTH-1
Table 2-29: Interrupt Address Vector Register Bit Definitions
Bit(s) Name
31:0 IRQ_VECTOR
1. C_INTC_BASE_VECTORS + 0x10
PITx Preload Register (PITx_PRELOAD) (x = 1, 2, 3 or 4)
The value written to this register determines the period between two consecutive
PITx_Interrupt events. The period is the value written to the register + 2 count events. The
register is implemented if C_USE_PITx is 1.
Table 2-30: PITx Preload Register (PITx_PRELOAD)
31
Table 2-31: PITx Preload Register Bit Definitions
Bit(s)
31:C_PITx_SIZE
[C_PITx_SIZE-1]:0
I/O Module v1.02a
PG052 October 16, 2012
Core Reset
Access Value
(1)
W The Interrupt Address Vector for the corresponding interrupt.
Reserved
Name
-
PITx_PRELOAD
www.xilinx.com
IRQ_VECTOR_x
Description
C_PITx_SIZE C_PITx_SIZE-1
Core Reset
Access Value
- - Reserved
W 0 Register holds the timer period
Register Space
0
2 1 0
PITx_PRELOAD
0
Description
21
Product Specification