Chapter 6: Customizing And Generating The Core; Gui - Xilinx LogiCORE IP v1.02a Product Manual

Customizing and Generating the Core
This chapter includes information on using Xilinx tools to customize and generate the core
in the ISE® Design Suite.

GUI

The I/O Module parameters are divided in seven tabs: System, UART, FIT Timers, PIT Timers,
GPO, GPI and Interrupt.
The System tab showing the Addresses parameters is shown in
X-Ref Target - Figure 6-1
• I/O Module Register Base Address - Base address of the internal registers.
• I/O Module Register High Address - High address of the internal registers.
I/O Module v1.02a
PG052 October 16, 2012
Figure 6-1: System Tab
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Chapter 6
Figure 6-1.
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