Xilinx LogiCORE IP v1.02a Product Manual page 12

Table 2-3: I/O Module I/O Signals (Cont'd)
Port Name
(1)
PITx_Enable
(1)
PITx_Interrupt
(1)
PITx_Toggle
(1)
GPOx
(1)
GPIx
(1)
GPIx_Interrupt
INTC_Interrupt
INTC_IRQ
INTC_Interrupt_Address [C_INTC_ADDR_WIDTH-1]:0
INTC_Interrupt_Ack
1. x = 1, 2, 3 or 4
Parameter - Port Dependencies
The width of many of the I/O Module signals depends on design parameters. The
dependencies between the design parameters and I/O signals are shown in
Table 2-4: Parameter-Port Dependencies
Parameter Name
C_INTC_INTR_SIZE
C_INTC_ADDR_WIDTH
C_GPO1_SIZE
C_GPO2_SIZE
C_GPO3_SIZE
C_GPO4_SIZE
C_GPI1_SIZE
C_GPI2_SIZE
C_GPI3_SIZE
C_GPI4_SIZE
I/O Module v1.02a
PG052 October 16, 2012
MSB:LSB
GPO Signals
[C_GPOx_SIZE - 1]:0
GPI Signals
[C_GPIx_SIZE - 1]:0
[C_GPIx_SIZE - 1]:0
INTC Signals
0:[C_INTC_INTR_SIZE - 1]
1:0
Ports (Port width depends on parameter)
INTC_Interrupt
INTC_Interrupt_Address
GPO1
GPO2
GPO3
GPO4
GPI1
GPI2
GPI3
GPI4
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I/O Description
I PITx count enable when C_PITx_PRESCALER
= External
O PITx timer lapsed
O Inverted PITx_Toggle when PITx lapses
GPOx Output
O
I GPIx Input
GPIx input changed
O
I External interrupt inputs
O Interrupt Output
Interrupt Address Output
O
Interrupt Acknowledge Input
I
Port Descriptions
Table 2-4.
12
Product Specification