Xilinx LogiCORE IP v1.02a Product Manual
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Xilinx LogiCORE IP v1.02a Product Manual

Xilinx LogiCORE IP v1.02a Product Manual

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LogiCORE IP I/O
Module v1.02a
Product Guide
PG052 October 16, 2012

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Summary of Contents for Xilinx LogiCORE IP v1.02a

  • Page 1 LogiCORE IP I/O Module v1.02a Product Guide PG052 October 16, 2012...

  • Page 2: Table Of Contents

    Device, Package, and Speed Grade Selections......... . 40 I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 3 Xilinx Resources ........

  • Page 4: Section I: Summary

    SECTION I: SUMMARY IP Facts Overview Product Specification Designing with the Core I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 5 LMB v1.0 bus interfaces to communicate Standalone S/W Driver with MicroBlaze Tested Design Flows • I/O Bus Design Entry Xilinx Platform Studio (XPS) • Interrupt Controller with fast interrupt Simulation Mentor Graphics ModelSim mode support Xilinx Synthesis Technology (XST) Synthesis •...
  • Page 6 GPIx_Interrupt PITx_Enable FITx_Toggle PITx_Toggle GPIx_IO GPOx_IO INTC_Interrupt INTC_IRQ INTC_Interrupt_Address Interrupt INTC_Interrupt_Ack Figure 1-1: I/O Module Block Diagram In a MicroBlaze system the I/O Module would typically be connected according to Figure 1-2. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 7: Feature Summary

    MicroBlaze Load/Store instructions. I/O Bus data is 32-bit wide, with byte enables to write byte and half-word data. The I/O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP). UART The Universal Asynchronous Receiver Transmitter (UART) interface provides the controller interface for asynchronous serial data transfers.

  • Page 8: Licensing And Ordering Information

    Programmable Interval Timers, or the General Purpose Inputs. Licensing and Ordering Information This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado Design Suite and ISE Design Suite Embedded Edition tools under the terms of the...

  • Page 9: Standards

    Chapter 2 Product Specification Standards The I/O Bus interface provided by the I/O Module is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP). For a detailed description of the DRP, see the 7 Series FPGAs Configuration User Guide [Ref...

  • Page 10: Resource Utilization

    All parameters not given in the table below have their default values. Table 2-2: Performance and Resource Utilization Benchmarks on Virtex-6 (xc6vlx240t-1-ff1156) Parameter Values (other parameters at default value) Device Resources LUTs Flip-Flops 65000 65000 65000 65000 I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...

  • Page 11: Port Descriptions

    Ready handshake to end I/O Bus access UART Signals UART_Rx_IO Receive Data UART_Tx_IO Transmit Data UART_Interrupt UART Interrupt FIT Signals FITx_Interrupt FITx timer lapsed FITx_Toggle Inverted FITx_Toggle when FITx timer lapses PIT Signals I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 12 Table 2-4: Parameter-Port Dependencies Parameter Name Ports (Port width depends on parameter) C_INTC_INTR_SIZE INTC_Interrupt C_INTC_ADDR_WIDTH INTC_Interrupt_Address C_GPO1_SIZE GPO1 C_GPO2_SIZE GPO2 C_GPO3_SIZE GPO3 C_GPO4_SIZE GPO4 C_GPI1_SIZE GPI1 C_GPI2_SIZE GPI2 C_GPI3_SIZE GPI3 C_GPI4_SIZE GPI4 I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...

  • Page 13: Register Space

    PIT3_CONTROL C_BASEADDR + 0x6C Reserved C_BASEADDR + 0x70 PIT4_PRELOAD PIT4 Preload Register C_BASEADDR + 0x74 PIT4_COUNTER PIT4 Counter Register PIT4 Control Register C_BASEADDR + 0x78 PIT4_CONTROL C_BASEADDR + 0x7C Reserved I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 14 Table 2-8: UART Transmit Data Register (UART_TX) (C_DATA_BITS=8) Reserved UART_TX Table 2-9: UART Transmit Data Register Bit Definitions Core Reset Bit(s) Name Description Access Value 31:C_UART_DATA_BITS Reserved [C_UART_DATA_BITS-1]:0 UART_TX UART Transmit Data I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 15 1= Transmit register is in use Reserved Reserved Indicates if the receive register has valid data Rx Valid Data 0 = Receive register is empty 1 = Receive register has valid data I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 16 This register reads the value that is input on the corresponding I/O Module GPIx port input signal bits. This register is not implemented if the value of C_USE_GPIx is 0. Table 2-16: General Purpose Input x Register (GPIx) Reserved GPIx C_GPIx_SIZE C_GPIx_SIZE-1 I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 17 FIT3 strobe FIT2 strobe FIT2 FIT1 FIT1 strobe PIT4 PIT4 lapsed PIT3 PIT3 lapsed PIT2 lapsed PIT2 PIT1 PIT1 lapsed UART_RX UART Received Data UART_TX UART Transmitted Data UART Error UART_ERR I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 18 FIT3 strobe FIT2 FIT2 strobe FIT1 strobe FIT1 PIT4 PIT4 lapsed PIT3 PIT3 lapsed PIT2 lapsed PIT2 PIT1 PIT1 lapsed UART_RX UART Received Data UART_TX UART Transmitted Data UART Error UART_ERR I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 19 PIT4 interrupt enabled PIT3 PIT3 interrupt enabled PIT2 interrupt enabled PIT2 PIT1 PIT1 interrupt enabled UART_RX UART Received Data interrupt enabled UART Transmitted Data interrupt enabled UART_TX UART_ERR UART Error interrupt enabled I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 20 Table 2-26: Interrupt Mode Register (IRQ_MODE) IRQ_MODE Table 2-27: Interrupt Mode Register Bit Definitions Core Reset Bit(s) Name Description Access Value 31:0 IRQ_MODE All bit positions written with 1 use fast interrupt mode I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 21 Table 2-30: PITx Preload Register (PITx_PRELOAD) Reserved PITx_PRELOAD C_PITx_SIZE C_PITx_SIZE-1 Table 2-31: PITx Preload Register Bit Definitions Core Reset Bit(s) Name Description Access Value 31:C_PITx_SIZE Reserved [C_PITx_SIZE-1]:0 PITx_PRELOAD Register holds the timer period I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...
  • Page 22 0 = Counter counts PITx_PRELOAD value cycles and the stops 1 = Counter value is automatically reloaded with the PITx_PRELOAD value when counter lapses 0 = Counting Disabled 1 = Counter Enabled I/O Module v1.02a www.xilinx.com PG052 October 16, 2012 Product Specification...

  • Page 23: Chapter 3: Designing With The Core

    IO_Read_Data is sampled at the rising Clk edge, when the slave has asserted IO_Ready. I/O Bus read and write transactions can be found in the two following timing diagrams in Figure 3-1 Figure 3-2. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 24 MicroBlaze endianess. Table 3-1: Valid Values for IO_Byte_Enable[3:0] IO_Byte_Enable IO_Data_Write and IO_Data_Read Byte Lanes Used [3:0] [31:24] [23:16] [15:8] [7:0] 0001 0010 0100 1000 0011 1100 1111 I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 25 General Design Guidelines The I/O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP). This configuration port supports partial dynamic reconfiguration of functional blocks, such as CMTs, clock management, XADC, serial transceivers, and the PCIe® block. The nominal connection of the I/O Bus to the DRP is shown in Table 3-2.
  • Page 26 PITx_Enable input. Using the parameter C_PITx_INTERRUPT, the PIT can be connected to the Interrupt Controller of the I/O Module and used for generating interrupts every time it lapses. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 27 0 -> 1 The current status of all interrupt sources can be read from the Interrupt Status Register. The current status of all enabled interrupts can be read from the Interrupt Pending Register. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 28: Lmb Timing

    Clocking The I/O Module is fully synchronous with all clocked elements clocked with the Clk input. Resets The Rst input is the master reset input signal for the I/O Module. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 29: Protocol Description

    Protocol Description Protocol Description See LMB Interface Description timing diagrams in the MicroBlaze Processor Reference Guide [Ref I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 30: Section Ii: Vivado Design Suite

    SECTION II: VIVADO DESIGN SUITE Customizing and Generating the Core Constraining the Core I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 31: Chapter 4: Customizing And Generating The Core

    Chapter 4 Customizing and Generating the Core This chapter includes information on using Xilinx tools to customize and generate the core in the Vivado™ Design Suite. The I/O Module parameters are divided in seven tabs: System, UART, FIT Timers, PIT Timers, GPO, GPI and Interrupt.
  • Page 32 • Programmable Baud Rate - Determines if the UART baud rate is programmable. The default baud rate is calculated based on the input clock frequency and the defined baud rate. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 33 Use FIT - Enable the Fixed Interval Timer. • Number of Clocks Between Strobes - The number of clock cycles between each strobe. • Generate Interrupt - Generate an interrupt for each Fixed Interval Timer strobe. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 34 Generate Interrupt - Generate an interrupt when the Programmable Interval Timer has counted down to zero. The GPO parameter tab showing the parameters for one of the four General Purpose Output ports is shown in Figure 4-5. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 35 0 of the port, the next right most to bit 1, and so on. The GPI parameter tab showing the parameters for one of the four General Purpose Input ports is shown in Figure 4-6. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 36 Number of Bits - Set the number of bits of the General Purpose Input port. • Generate Interrupt - Generate an interrupt when a General Purpose Input changes. The Interrupt parameter tab is shown in Figure 4-7. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 37: Parameter Values

    I/O module design. This allows for configuring a design that only uses the resources required by the system, and operates with the best possible performance. The features that can be parameterized in I/O Module designs are shown in Table 4-1. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 38 0 = Not Used integer 1 = Used C_PITx_SIZE Size of PITx counter 1 - 32 integer C_PITx_READABLE Make PITx counter software 0 = Not SW integer readable readable 1 = SW readable I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 39 2. x =1, 2, 3 or 4. 3. Selecting PIT prescaler the same as PITx is illegal, e.g. PIT2 cannot be prescaler to itself. 4. The 7 least significant bits must all be 0. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 40: Chapter 5: Constraining The Core

    The I/O Module is fully synchronous with all clocked elements clocked by the Clk input. To operate properly when connected to MicroBlaze™, the Clk must be the same as the MicroBlaze Clk. Clock Placement There are no specific Clock placement requirements for this core. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 41: Banking

    There are no specific Banking rules for this core. Transceiver Placement There are no Transceiver Placement requirements for this core. I/O Standard and Placement There are no specific I/O standards and placement requirements for this core. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 42: Section Iii: Ise Design Suite

    SECTION III: ISE DESIGN SUITE Customizing and Generating the Core Constraining the Core I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 43: Chapter 6: Customizing And Generating The Core

    Chapter 6 Customizing and Generating the Core This chapter includes information on using Xilinx tools to customize and generate the core in the ISE® Design Suite. The I/O Module parameters are divided in seven tabs: System, UART, FIT Timers, PIT Timers, GPO, GPI and Interrupt.
  • Page 44 (stdout) in the software program. • Define Baud Rate - Sets the UART baud rate. To get the correct baud rate, the input clock frequency must also be correctly defined. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 45 The FIT Timer parameter tab showing the parameters for one of the four timers is shown in Figure 6-3. X-Ref Target - Figure 6-3 Figure 6-3: FIT Timers Parameter Tab • Use FIT - Enable the Fixed Interval Timer. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 46 Generate Interrupt - Generate an interrupt when the Programmable Interval Timer has counted down to zero. The GPO parameter tab showing the parameters for one of the four General Purpose Output ports is shown in Figure 6-5. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 47 0 of the port, the next right most to bit 1, and so on. The GPI parameter tab showing the parameters for one of the four General Purpose Input ports is shown in Figure 6-6. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...
  • Page 48 Use GPI - Enable the General Purpose Input port. • Number of Bits - Set the number of bits of the General Purpose Input port. • Generate Interrupt - Generate an interrupt when a General Purpose Input changes. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 49: Parameter Values

    I/O module design. This allows the user to configure a design that only utilizes the resources required by the system, and operates with the best possible performance. The specific features that can be parameterized in Xilinx I/O Module EDK designs are shown in Table 6-1.
  • Page 50 , and the n least significant bits of BASEADDR must be zero. 3. The decode mask determines which bits are used by the LMB decode logic to decode a valid access to LMB. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 51: Chapter 7: Constraining The Core

    The I/O Module is fully synchronous with all clocked elements clocked by the Clk input. To operate properly when connected to MicroBlaze™, the Clk must be the same as the MicroBlaze Clk. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 52: Section Iv: Appendices

    SECTION IV: APPENDICES Migrating Debugging Application Software Development Additional Resources I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 53: Appendix A: Migrating

    This appendix describes migrating from older versions of the IP to the current IP release. For information on migrating to the Vivado™ Design Suite, see the Vivado Design Suite Migration Methodology Guide [Ref I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 54: Appendix B: Debugging

    Appendix B Debugging Solution Centers See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips. Shortened Title with Core Version www.xilinx.com...

  • Page 55: Appendix C: Application Software Development

    Appendix C Application Software Development Device Drivers The I/O Module is supported by the IO Module driver, included with Xilinx Software Development Kit. I/O Module v1.02a www.xilinx.com PG052 October 16, 2012...

  • Page 56: Appendix D: Additional Resources

    LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

  • Page 57: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

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