Xilinx LogiCORE IP v1.02a Product Manual page 25

The I/O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP). This
configuration port supports partial dynamic reconfiguration of functional blocks, such as
CMTs, clock management, XADC, serial transceivers, and the PCIe® block.
The nominal connection of the I/O Bus to the DRP is shown in
Table 3-2: Mapping of the I/O Bus to the Dynamic Reconfiguration Port
MicroBlaze MCS Signal
Clk
IO_Addr_Strobe
IO_Read_Strobe
IO_Write_Strobe
IO_Address[m+2:2]
IO_Byte_Enable
IO_Write_Data[n:0]
IO_Read_Data[n:0]
IO_Ready
For a detailed description of the DRP, see the 7 Series FPGAs Configuration User Guide
[Ref 2].
UART
The Universal Asynchronous Receiver Transmitter (UART) interface provides the controller
interface for asynchronous serial data transfers. Features supported include:
• One transmit and one receive channel (full duplex)
• Configurable number of data bits in a character (5-8)
• Configurable parity bit (odd or even)
• Configurable and programmable baud rate
The UART performs parallel-to-serial conversion on characters received through LMB and
serial-to-parallel conversion on characters received from a serial peripheral. The UART is
capable of transmitting and receiving 8, 7, 6 or 5-bit characters, with 1-stop bit and odd,
even or no parity. The UART can transmit and receive independently.
The device can be configured and its status can be monitored via the internal register set.
The UART also asserts the UART_Interrupt output when the receiver becomes
non-empty, when the transmitter becomes empty or when an error condition has occurred.
The individual interrupt events are connected to the Interrupt Controller of the I/O Module
and can be used to assert the INTC_IRQ output signal.
I/O Module v1.02a
PG052 October 16, 2012
DRP Signal
DCLK
DEN
-
DWE
DADDR[m:0]
-
DI[n:0]
DO[n:0]
DRDY
www.xilinx.com
General Design Guidelines
Table 3-2.
Note
Not used by DRP
Uses 32-bit word access for DRP
Only 32-bit word accesses used for DRP
Data width depends on DRP (n < 32)
Data width depends on DRP (n < 32)
25