Mov32 Rah, Xarn Move The Contents Of Xarn To A 32-Bit Floating-Point Register - Texas Instruments TMS320C28 series Reference Manual

Instructions
MOV32 RaH, XARn
Move the Contents of XARn to a 32-bit Floating-Point Register
Operands
RaH
XARn
Opcode
LSW: 1011 1101
MSW: IIII IIII
Move the 32-bit value in the auxiliary register XARn to the floating point register RaH.
Description
RaH = XARn
This instruction does not modify any STF register flags.
Flags
Flag
Modified
While this is a single-cycle instruction, additional pipeline alignment is required. Four
Pipeline
alignment cycles are required after any copy from a standard 28x CPU register to a
floating-point register. The four alignment cycles can be filled with any non-conflicting
instructions except for the following: FRACF32, UI16TOF32, I16TOF32, F32TOUI32,
and F32TOI32.
Example
MOV32 RaH, ACC
See also
MOV32 RaH, P
MOV32 RaH, XT
90 Instruction Set
floating-point register (R0H to R7H)
auxiliary register (XAR0 - XAR7)
loc32
IIII IIII
TF ZI
No No
MOV32 R0H,@XAR7
NOP
NOP
NOP
NOP
ADDF32 R2H,R1H,R0H
MOVL XAR1, #0x0200 ; XAR1 = 512
MOV32 R0H, XAR1
NOP
NOP
NOP
NOP
UI32TOF32 R0H, R0H ; R0H = 512.0 (0x44000000)
NI ZF NF
No No No
; Copy XAR7 to R0H
; Wait 4 alignment cycles
; Do not use FRACF32, UI16TOF32
; I16TOF32, F32TOUI32 or F32TOI32
;
; <-- R0H is valid
; Instruction can use R0H as a source
SPRUEO2A – June 2007 – Revised August 2008
www.ti.com
LUF LVF
No No
Submit Documentation Feedback