Mpyf32 Rah, #16Fhi, Rbh 32-Bit Floating-Point Multiply - Texas Instruments TMS320C28 series Reference Manual

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MPYF32 RaH, #16FHi, RbH
Operands
RaH
#16FHi
RcH
Opcode
LSW: 1110 1000
MSW: IIII IIII
Multiply RbH with the floating-point value represented by the immediate operand. Store
Description
the result of the addition in RaH.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
RaH = RbH * #16FHi:0
This instruction can also be written as MPYF32 RaH, RbH, #16FHi.
This instruction modifies the following flags in the STF register:.
Flags
Flag
Modified
The STF register flags are modified as follows:
• LUF = 1 if MPYF32 generates an underflow condition.
• LVF = 1 if MPYF32 generates an overflow condition.
This is a 2 pipeline cycle (2p) instruction. That is:
Pipeline
Any instruction in the delay slot must not use RaH as a destination register or use RaH
as a source operand.
Example 1
Example 2
;Same as above example but #16FHi is represented in Hex
MPYF32 RaH, RbH, #16FHi
See also
MPYF32 RaH, RbH, RcH
MPYF32 RaH, RbH, RcH || ADDF32 RdH, ReH, RfH
SPRUEO2A – June 2007 – Revised August 2008
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32-bit Floating-Point Multiply
floating-point destination register (R0H to R7H)
A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0.
floating-point source register (R0H to R7H)
01II IIII
IIbb baaa
TF ZI
No No
MPYF32 RaH, #16FHi, RbH ; 2 pipeline cycles (2p)
NOP
NOP
MOVIZF32 R3H, #2.0
MPYF32 R4H, #3.0, R3H
MOVL XAR1, #0xB006
MOV32 *XAR1, R4H
MOVIZF32 R3H, #2.0
MPYF32 R4H, #0x4040, R3H
MOVL XAR1, #0xB006
MOV32 *XAR1, R4H
NI ZF NF
No No No
; 1 cycle delay or non-conflicting instruction
; <-- MPYF32 completes, RaH updated
; R3H = 2.0 (0x40000000)
; R4H = 3.0 * R3H
; <-- Non conflicting instruction
; <-- MPYF32 complete, R4H = 6.0 (0x40C00000)
; Save the result in memory location 0xB006
; R3H = 2.0 (0x40000000)
; R4H = 0x4040 * R3H
; 3.0 is represented as 0x40400000 in
; IEEE 754 32-bit format
; <-- Non conflicting instruction
; <-- MPYF32 complete, R4H = 6.0 (0x40C00000)
; Save the result in memory location 0xB006
Instructions
LUF LVF
Yes Yes
Instruction Set 103