Einvf32 Rah, Rbh 32-Bit Floating-Point Reciprocal Approximation - Texas Instruments TMS320C28 series Reference Manual

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EINVF32 RaH, RbH
32-bit Floating-Point Reciprocal Approximation
Operands
RaH
RbH
Opcode
LSW: 1110 0110
MSW: 0000 0000
This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
Description
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:
Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X)
Ye = Ye*(2.0 - Ye*X)
After 2 iterations of the Newton-Raphson algorithm, you will get an exact answer
accurate to the 32-bit floating-point format. On each iteration the mantissa bit accuracy
approximately doubles. The EINVF32 operation will not generate a negative zero,
DeNorm or NaN value.
RaH = Estimate of 1/RbH
This instruction modifies the following flags in the STF register:
Flags
Flag
Modified
The STF register flags are modified as follows:
• LUF = 1 if EINVF32 generates an underflow condition.
• LVF = 1 if EINVF32 generates an overflow condition.
This is a 2 pipeline cycle (2p) instruction. That is:
Pipeline
Any instruction in the delay slot must not use RaH as a destination register or use RaH
as a source operand.
SPRUEO2A – June 2007 – Revised August 2008
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floating-point destination register (R0H to R7H)
floating-point source register (R0H to R7H)
1001 0011
00bb baaa
TF ZI
No No
EINVF32 RaH, RbH
NOP
NOP
NI ZF NF
No No No
; 2p
; 1 cycle delay or non-conflicting instruction
; <-- EINVF32 completes, RaH updated
Instructions
LUF LVF
Yes Yes
Instruction Set 47