Pipeline - Texas Instruments TMS320C28 series Reference Manual

The pipeline flow for C28x instructions is identical to that of the C28x CPU described in TMS320C28x
DSP CPU and Instruction Set Reference Guide (SPRU430). Some floating-point instructions, however,
use additional execution phases and thus require a delay to allow the operation to complete. This pipeline
alignment is achieved by inserting NOPs or non-conflicting instructions when required. Software control of
delay slots allows you to improve performance of an application by taking advantage of the delay slots and
filling them with non-conflicting instructions. This section describes the key characteristics of the pipeline
with regards to floating-point instructions. The rules for avoiding pipeline conflicts are small in number and
simple to follow and the C28x+FPU assembler will help you by issuing errors for conflicts.
..................................................................................................
Topic
3.1
3.2
3.3
3.4
3.5
3.6
3.7
SPRUEO2A – June 2007 – Revised August 2008
Submit Documentation Feedback
.....................................................................
Pipeline Overview
General Guidelines for Floating-Point Pipeline Alignment
Moves from FPU Registers to C28x Registers
Moves from C28x Registers to FPU Registers
..................................................................
Parallel Instructions
Invalid Delay Instructions
Optimizing the Pipeline
SPRUEO2A – June 2007 – Revised August 2008
..............................
..............................
...........................................................
..............................................................
Chapter 3

Pipeline

Page
22
..............
22
23
23
24
24
27
Pipeline 21