Mpyf32 Rah, Rbh, Rch Addf32 Rdh, Reh, Rfh 32-Bit Floating-Point Multiply With Parallel Add - Texas Instruments TMS320C28 series Reference Manual

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MPYF32 RaH, RbH, RcH
ADDF32 RdH, ReH, RfH
Operands
RaH
RbH
RcH
RdH
ReH
RfH
Opcode
LSW: 1110 0111
MSW: feee dddc
Multiply the contents of two floating-point registers with parallel addition of two registers.
Description
RaH = RbH * RcH
RdH = ReH + RfH
This instruction can also be written as:
MACF32 RaH, RbH, RcH, RdH, ReH, RfH
The destination register for the MPYF32 and the ADDF32 must be unique. That is, RaH
Restrictions
cannot be the same register as RdH.
This instruction modifies the following flags in the STF register:.
Flags
Flag
Modified
The STF register flags are modified as follows:
• LUF = 1 if MPYF32 or ADDF32 generates an underflow condition.
• LVF = 1 if MPYF32 or ADDF32 generates an overflow condition.
Both MPYF32 and ADDF32 take 2 pipeline cycles (2p) That is:
Pipeline
Any instruction in the delay slot must not use RaH or RdH as a destination register or as
a source operand.
SPRUEO2A – June 2007 – Revised August 2008
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32-bit Floating-Point Multiply with Parallel Add
floating-point destination register for MPYF32 (R0H to R7H)
RaH cannot be the same register as RdH
floating-point source register for MPYF32 (R0H to R7H)
floating-point source register for MPYF32 (R0H to R7H)
floating-point destination register for ADDF32 (R0H to R7H)
RdH cannot be the same register as RaH
floating-point source register for ADDF32 (R0H to R7H)
floating-point source register for ADDF32 (R0H to R7H)
0100 00ff
ccbb baaa
TF ZI
No No
MPYF32 RaH, RbH, RcH
|| ADDF32 RdH, ReH, RfH
NOP
NOP
NI ZF NF
No No No
; 2 pipeline cycles (2p)
; 2 pipeline cycles (2p)
; 1 cycle delay or non-conflicting instruction
; <-- MPYF32, ADDF32 complete, RaH, RdH updated
Instructions
LUF LVF
Yes Yes
Instruction Set 105