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ADDF32 RaH, RbH, RcH
Operands
RaH
RbH
RcH
Opcode
LSW: 1110 0111
MSW: 0000 000c
Add the contents of RcH to the contents of RbH and load the result into RaH.
Description
RaH = RbH + RcH
This instruction modifies the following flags in the STF register:
Flags
Flag
Modified
The STF register flags are modified as follows:
• LUF = 1 if ADDF32 generates an underflow condition.
• LVF = 1 if ADDF32 generates an overflow condition.
This is a 2 pipeline-cycle instruction (2p). That is:
Pipeline
Any instruction in the delay slot must not use RaH as a destination register or use RaH
as a source operand.
Calculate Y = M1*X1 + B1. This example assumes that M1, X1, B1 and Y are all on the
Example
same data page.
|| MOV32
Calculate Y = A + B.
ADDF32 RaH, #16FHi, RbH
See also
ADDF32 RaH, RbH, #16FHi
ADDF32 RdH, ReH, RfH || MOV32 RaH, mem32
ADDF32 RdH, ReH, RfH || MOV32 mem32, RaH
MACF32 R3H, R2H, RdH, ReH, RfH
MPYF32 RaH, RbH, RcH || ADDF32 RdH, ReH, RfH
SPRUEO2A – June 2007 – Revised August 2008
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32-bit Floating-Point Addition
floating-point destination register (R0H to R7H)
floating-point source register (R0H to R7H)
floating-point source register (R0H to R7H)
0001 0000
ccbb baaa
TF
ZI
No
No
ADDF32 RaH, RbH, RcH
NOP
NOP
MOVW
DP, #M1
; Load the data page
MOV32
R0H,@M1
; Load R0H with M1
MOV32
R1H,@X1
; Load R1H with X1
MPYF32
R1H,R1H,R0H
; Multiply M1*X1
R0H,@B1
;
NOP
; <-- MOV32 complete
; <-- MPYF32 complete
ADDF32
R1H,R1H,R0H
; Add M*X1 to B1 and store in R1H
NOP
; <-- ADDF32 complete
MOV32
@Y1,R1H
; Store the result
MOVL
XAR4, #A
MOV32
R0H,
*XAR4
; Load R0H with A
MOVL
XAR4, #B
MOV32
R1H,
*XAR4
; Load R1H with B
ADDF32 R0H,R1H,R0H
; Add A + B R0H=R0H+R1H
MOVL
XAR4, #Y
; <-- ADDF32 complete
MOV32 *XAR4,R0H
; Store the result
NI
ZF
NF
No
No
No
; 2 pipeline cycles (2p)
; 1 cycle delay or non-conflicting instruction
; <-- ADDF32 completes, RaH updated
and in parallel load R0H with B1
Instructions
LUF
LVF
Yes
Yes
Instruction Set
39
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