Table Of Contents - Texas Instruments TMS320C28 series Reference Manual

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Preface
1 Introduction
1.1 Introduction to the Central Processing Unit (CPU)
1.2 Compatibility with the C28x Fixed-Point CPU
1.2.1 Floating-Point Code Development
1.3 Components of the C28x plus Floating-Point CPU
1.3.1 Emulation Logic
1.3.2 Memory Map
1.3.3 On-Chip Program and Data
1.3.4 CPU Interrupt Vectors
1.4 Memory Interface
1.4.1 Address and Data Buses
1.4.2 Alignment of 32-Bit Accesses to Even Addresses
2 CPU Register Set
2.1 CPU Registers
2.1.1 Floating-Point Status Register (STF)
2.1.2 Repeat Block Register (RB)
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3 Pipeline
3.1 Pipeline Overview
3.2 General Guidelines for Floating-Point Pipeline Alignment
3.3 Moves from FPU Registers to C28x Registers
3.4 Moves from C28x Registers to FPU Registers
3.5 Parallel Instructions
3.6 Invalid Delay Instructions
3.7 Optimizing the Pipeline
4 Instruction Set
4.1 Instruction Descriptions
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4.2 Instructions
A Revision History
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A.1 Changes
SPRUEO2A - June 2007 - Revised August 2008
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Contents
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