Macf32 R7H, R6H, Rdh, Reh, Rfh 32-Bit Floating-Point Multiply With Parallel Add - Texas Instruments TMS320C28 series Reference Manual

Instructions
MACF32 R7H, R6H, RdH, ReH, RfH
This instruction is an alias for the parallel multiply and add instruction. The operands are
Operands
translated by the assembler such that the instruction becomes:
R7H
R6H
RdH
ReH
RfH
Opcode
LSW: 1110 0111
MSW: feee dddc
This instruction is an alias for the parallel multiply and add, MACF32 || ADDF32,
Description
instruction.
RdH = RaH * RbH
R7H = R6H + R6H
The destination register for the MPYF32 and the ADDF32 must be unique. That is, RdH
Restrictions
cannot be R7H.
This instruction modifies the following flags in the STF register:.
Flags
Flag
Modified
The STF register flags are modified as follows:
• LUF = 1 if MPYF32 or ADDF32 generates an underflow condition.
• LVF = 1 if MPYF32 or ADDF32 generates an overflow condition.
Both MPYF32 and ADDF32 take 2 pipeline cycles (2p) That is:
Pipeline
Any instruction in the delay slot must not use RaH or RdH as a destination register or as
a source operand.
68 Instruction Set
32-bit Floating-Point Multiply with Parallel Add
MPYF32 RdH, RaH, RbH
|| ADDF32 R7H, R7H, R6H
floating-point destination and source register for the ADDF32
floating-point source register for the ADDF32 operation (R0H to R7H)
floating-point destination register for MPYF32 operation (R0H to R7H)
RdH cannot be R3H
floating-point source register for MPYF32 operation (R0H to R7H)
floating-point source register for MPYF32 operation (R0H to R7H)
0100 00ff
ccbb baaa
TF ZI
No No
MPYF32 RaH, RbH, RcH
|| ADDF32 RdH, ReH, RfH
NOP
NOP
NI ZF NF
No No No
; 2 pipeline cycles (2p)
; 2 pipeline cycles (2p)
; 1 cycle delay or non-conflicting instruction
; <-- MPYF32, ADDF32 complete, RaH, RdH updated
SPRUEO2A – June 2007 – Revised August 2008
www.ti.com
LUF LVF
Yes Yes
Submit Documentation Feedback