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Texas Instruments TMS320DM357 User Manual

Dmsoc universal serial bus (usb) controller
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TMS320DM357 DMSoC Universal Serial Bus
(USB) Controller
User's Guide
Literature Number: SPRUGH3
November 2008

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Summary of Contents for Texas Instruments TMS320DM357

  • Page 1 TMS320DM357 DMSoC Universal Serial Bus (USB) Controller User's Guide Literature Number: SPRUGH3 November 2008...
  • Page 2 SPRUGH3 – November 2008 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Preface Introduction Purpose of the Peripheral Features Features Not Supported Functional Block Diagram Supported Use Case Examples Industry Standard(s) Compliance Statement Peripheral Architecture Clock Control Signal Descriptions Indexed and Non-Indexed Registers USB PHY Initialization Dynamic FIFO Sizing USB Controller Host and Peripheral Modes Operation USB Controller Peripheral Mode Operation USB Controller Host Mode Operation DMA Operation...
  • Page 4 4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) 4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) 4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) 4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) 4.21 Receive CPPI Control Register (RCPPICR) 4.22 Receive CPPI Masked Status Register (RCPPIMSKSR) 4.23 Receive CPPI Raw Status Register (RCPPIRAWSR) 4.24...
  • Page 5 www.ti.com 4.66 Type Register (Host mode only) (HOST_TYPE0) 4.67 Transmit Type Register (Host mode only) (HOST_TXTYPE) 4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) 4.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) 4.70 Receive Type Register (Host mode only) (HOST_RXTYPE) 4.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) 4.72 Configuration Data Register (CONFIGDATA)
  • Page 6 Functional Block Diagram Interrupt Service Routine Flow Chart CPU Actions at Transfer Phases Sequence of Transfer Service Endpoint 0 Flow Chart IDLE Mode Flow Chart TX Mode Flow Chart RX Mode Flow Chart Setup Phase of a Control Transaction Flow Chart IN Data Phase Flow Chart OUT Data Phase Flow Chart Completion of SETUP or OUT Data Phase Flow Chart...
  • Page 7 www.ti.com Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) Receive CPPI Completion Pointer (RCPPICOMPPTR) Function Address Register (FADDR) Power Management Register (POWER)
  • Page 8 USB Pins PERI_TXCSR Register Bit Configuration for Bulk IN Transactions PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions Transmit Buffer Descriptor Word 0 Transmit Buffer Descriptor Word 1 Transmit Buffer Descriptor Word 2 Transmit Buffer Descriptor Word 3 Receive Buffer Descriptor Word 0...
  • Page 9 www.ti.com Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Field Descriptions Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) Field Descriptions Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) Field Descriptions Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Field Descriptions...
  • Page 10 Transmit Hub Port (TXHUBPORT) Field Descriptions Receive Function Address (RXFUNCADDR) Field Descriptions Receive Hub Address (RXHUBADDR) Field Descriptions Receive Hub Port (RXHUBPORT) Field Descriptions Document Revision History List of Tables www.ti.com SPRUGH3 – November 2008 Submit Documentation Feedback...

  • Page 11: Preface

    About This Manual This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
  • Page 12 User's Guide. Describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of applications to provide removable data storage. The MMC/SD controller provides an interface to external MMC and SD cards.
  • Page 13 SPRUG39 — TMS320DM357 DMSoC Video Processing Front End (VPFE) User's Guide. Describes the video processing front end (VPFE) in the TMS320DM357 Digital Media System-on-Chip (DMSoC) video processing subsystem. Included in the VPFE is the preview engine, CCD controller, resizer, histogram, and hardware 3A (H3A) statistic generator.

  • Page 14: Introduction

    Introduction This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The controller supports high-speed USB peripheral mode and high-speed limited host-mode operations. The USB controller can be operated by ARM through the memory-mapped registers.

  • Page 15: Functional Block Diagram

    www.ti.com Functional Block Diagram The USB functional block diagram is shown in Internal CPPI engine Registers, interrupts, endpoint control, SPRUGH3 – November 2008 Submit Documentation Feedback Figure Figure 1. Functional Block Diagram Packet FIFO encode/ decode and packet scheduling Introduction 24 MHz crystal oscillator...

  • Page 16: Supported Use Case Examples

    Introduction Supported Use Case Examples The USB supports the following user cases: Detailed information about the architecture and operation of the USB controller follows in Programming examples are also provided for each of the operational modes of the controller. User Case 1: An example of how to initialize the USB controller Example 1.
  • Page 17 www.ti.com User Case 2: An example of how to program the USB Endpoints in peripheral mode Example 2. Programming the USB Endpoints in Peripheral Mode // DMA channel number. Valid values are 0, 1, 2, or 3. int CHAN_NUM = 0; // Fifo sizes: uncomment the desired size.
  • Page 18 Introduction User Case 3: An example of how to program the USB endpoints in host mode Example 3. Programming the USB Endpoints in Host Mode // DMA channel number. Valid values are 0, 1, 2, or 3. int CHAN_NUM = 0; // Fifo sizes: uncomment the desired size.
  • Page 19 www.ti.com Example 3. Programming the USB Endpoints in Host Mode (continued) usbRegs->TXFIFOSZ = fifosize | ((double_buffer & 1)<<4); usbRegs->TXFIFOADDR = fifo_start_address + (1<<(fifosize+double_buffer)); usbRegs->RXMAXP = FIFO_MAXP; usbRegs->TXMAXP = FIFO_MAXP; //Configure the endpoint switch (device_speed) { case LOW_SPEED : type = (3<<6) | ((device_protocol & 3) << 4) | (device_ep & 0xf); break; case FULL_SPEED: type = (2<<6) | ((device_protocol &...
  • Page 20 Introduction User Case 4: An example of how to do host negotiation to support USB If the HOSTREQ bit in the DEVCTL register is set, host negotiation is performed by the hardware when the device enters suspend mode. The bit is cleared when host negotiation is complete. User Case 5: An example of how to program the USB DMA controller Example 4.
  • Page 21 www.ti.com Example 4. Programming the USB DMA Controller (continued) usbRegs->CHANNEL[i].RCPPIDMASTATEW6 = 0; tx_desc[i] = 0; rx_desc[i] = 0; // Routine to flush TX fifo. // Must call this routine twice for double-buffered FIFO void flush_tx_fifo(int ep) { int index_save; int status; index_save = usbRegs->INDEX;...

  • Page 22: Industry Standard(S) Compliance Statement

    Introduction Example 4. Programming the USB DMA Controller (continued) // Increment descriptor counter tx_desc[ch]++; // Routine to start the RX DMA for a given channel void start_rx_dma(int ch) { int index_save; index_save = usbRegs->INDEX; // Must have at least 3 descriptors to receive anything if (rx_desc[ch] <...

  • Page 23: Peripheral Architecture

    www.ti.com Peripheral Architecture Clock Control Information related to clock generation and control for the USB peripheral will be added in a future revision of this document. Clocks for USB are generated based on a crystal oscillator on the M24XI and M24XO pins.

  • Page 24: Usb Phy Initialization

    USB Controller Host and Peripheral Modes Operation USB PHY Initialization The following bits in USBPHY_CTL must be cleared to enable the USB controller: OSCPDWN and PHYPDWN. The following bits in USBPHY_CTL must be set to enable the level comparators: VBDTCTEN and VBUSENS.

  • Page 25: Interrupt Service Routine Flow Chart

    www.ti.com Figure 2. Interrupt Service Routine Flow Chart Resume routine Session req routine Vbus error routine Connect routine Babble routine Host EP0 routine Host Rx routine Host Tx routine SPRUGH3 – November 2008 Submit Documentation Feedback USB Controller Host and Peripheral Modes Operation Read interrupt status register Resume...

  • Page 26: Usb Controller Peripheral Mode Operation

    USB Controller Host and Peripheral Modes Operation USB Controller Peripheral Mode Operation Soft connect - After a reset, the SOFTCONN bit of POWER register (bit 6) is cleared to 0. The controller will therefore appear disconnected until the software has set the SOFTCONN bit to 1. The application software can then choose when to set the PHY into its normal mode.
  • Page 27 www.ti.com Note: The Setup packet associated with any standard device request should include an 8-byte command. Any setup packet containing a command field of anything other than 8 bytes will be automatically rejected by the controller. 3.1.1.1 Zero Data Requests Zero data requests have all their information included in the 8-byte command and require no additional data to be transferred.
  • Page 28 USB Controller Host and Peripheral Modes Operation If the length of the data associated with the request (indicated by the wLength field in the command) is greater than the maximum packet size for endpoint 0, further data packets will be sent. In this case, PERI_CSR0 should be written to set the SERV_RXPKTRDY bit, but the DATAEND bit should not be set.

  • Page 29: Cpu Actions At Transfer Phases

    www.ti.com 3.1.1.4 Endpoint 0 States When the USB controller is operating as a peripheral device, the endpoint 0 control needs three modes – IDLE, TX and RX – corresponding to the different phases of the control transfer and the states endpoint 0 enters for the different phases of the transfer (described in later sections).

  • Page 30: Sequence Of Transfer

    USB Controller Host and Peripheral Modes Operation Idle Sequence #1 Setup Unload device CPU actions req. and clear RxPktRdy Idle Sequence #2 Setup CPU actions No data phase Sequence #3 Setup Idle CPU actions Universal Serial Bus (USB) Controller Figure 4. Sequence of Transfer TX state IN data IN data...
  • Page 31 www.ti.com 3.1.1.5 Endpoint 0 Service Routine An Endpoint 0 interrupt is generated when: The controller sets the RXPKTRDY bit of PERI_CSR0 (bit 0) after a valid token has been received and data has been written to the FIFO. The controller clears the TXPKTRDY bit of PERI_CSR0 (bit 1) after the packet of data in the FIFO has been successfully transmitted to the host.

  • Page 32: Service Endpoint 0 Flow Chart

    USB Controller Host and Peripheral Modes Operation Read endpoint 0 CSR * By default Universal Serial Bus (USB) Controller Figure 5. Service Endpoint 0 Flow Chart Service endpoint 0 Sent Clear SentStall bit stall Setup Set ServicedSetupEnd State = IDLE State = TX State...

  • Page 33: Idle Mode Flow Chart

    www.ti.com 3.1.1.5.1 IDLE Mode IDLE mode is the mode the endpoint 0 control must select at power-on or reset and is the mode to which the endpoint 0 control should return when the RX and TX modes are terminated. It is also the mode in which the SETUP phase of control transfer is handled (as outlined in Decode command ServiceRxPktRdy...

  • Page 34: Tx Mode Flow Chart

    USB Controller Host and Peripheral Modes Operation 3.1.1.5.2 TX Mode When the endpoint is in TX state all arriving IN tokens need to be treated as part of a data phase until the required amount of data has been sent to the host. If either a SETUP or an OUT token is received while the endpoint is in the TX state, this will cause a SetupEnd condition to occur as the core expects only IN tokens.

  • Page 35: Rx Mode Flow Chart

    www.ti.com 3.1.1.5.3 RX Mode In RX mode, all arriving data should be treated as part of a data phase until the expected amount of data has been received. If either a SETUP or an IN token is received while the endpoint is in RX state, a SetupEnd condition will occur as the controller expects only OUT tokens.
  • Page 36 USB Controller Host and Peripheral Modes Operation 3.1.1.5.4 Error Handling A control transfer may be aborted due to a protocol error on the USB, the host prematurely ending the transfer, or if the software wishes to abort the transfer (e.g., because it cannot process the command). The controller automatically detects protocol errors and sends a STALL packet to the host under the following conditions: The host sends more data during the OUT Data phase of a write request than was specified in the...

  • Page 37: Peri_Txcsr Register Bit Configuration For Bulk In Transactions

    www.ti.com 3.1.2 Bulk Transactions 3.1.2.1 Peripheral Mode: Bulk In Transactions A Bulk IN transaction is used to transfer non-periodic data from the USB peripheral device to the host. The following optional features are available for use with a Tx endpoint used in peripheral mode for Bulk IN transactions: Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting transmission to the host.
  • Page 38 USB Controller Host and Peripheral Modes Operation 3.1.2.1.2 Operation When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet can be loaded into the FIFO.

  • Page 39: Peri_Rxcsr Register Bit Configuration For Bulk Out Transactions

    www.ti.com 3.1.2.2.1 Setup In configuring an Rx endpoint for Bulk OUT transactions, the RXMAXP register must be written with the maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In addition, the relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for this endpoint) and the PERI_RXCSR register should be set as shown in Table 3.
  • Page 40 USB Controller Host and Peripheral Modes Operation 3.1.2.2.3 Error Handling If the software wants to shut down the Bulk OUT pipe, it should set the SENDSTALL bit (bit 5 of PERI_RXCSR). When the controller receives the next packet it will send a STALL to the host, set the SENTSTALL bit (bit 6 of PERI_RXCSR) and generate an interrupt.

  • Page 41: Peri_Txcsr Register Bit Configuration For Isochronous In Transactions

    www.ti.com 3.1.4 Isochronous Transactions 3.1.4.1 Isochronous IN Transactions An Isochronous IN transaction is used to transfer periodic data from the function controller to the host. The following optional features are available for use with a Tx endpoint used in Peripheral mode for Isochronous IN transactions: Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting transmission to the host.
  • Page 42 USB Controller Host and Peripheral Modes Operation An interrupt is generated whenever a packet is sent to the host and the software may use this interrupt to load the next packet into the FIFO and set the TXPKTRDY bit in the PERI_TXCSR register (bit 0) in the same way as for a Bulk Tx endpoint.

  • Page 43: Peri_Rxcsr Register Bit Configuration For Isochronous Out Transactions

    www.ti.com 3.1.4.2.1 Setup In configuring an Rx endpoint for Isochronous OUT transactions, the RXMAXP register must be written with the maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In addition, the relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for this endpoint) and the PERI_RXCSR register should be set as shown in Table 5.

  • Page 44: Usb Controller Host Mode Operation

    USB Controller Host and Peripheral Modes Operation USB Controller Host Mode Operation Entry into Suspend mode. When operating as a host, the controller can be prompted to enter Suspend mode by setting the SUSPENDM bit in the POWER register. When this bit is set, the controller will complete the current transaction then stop the transaction scheduler and frame counter.

  • Page 45: Setup Phase Of A Control Transaction Flow Chart

    www.ti.com 3.2.1.1 Setup Phase For the SETUP Phase of a control transaction 1. Load the 8 bytes of the required Device request command into the Endpoint 0 FIFO. 2. Set SETUPPKT and TXPKTRDY (bits 3 and 1 of HOST_CSR0, respectively). Note: These bits must be set together.
  • Page 46 USB Controller Host and Peripheral Modes Operation 3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.

  • Page 47: In Data Phase Flow Chart

    www.ti.com NAK limit reached Error count cleared NAK Timeout set Endpoint halted Interrupt generated 3.2.1.3 OUT Data Phase For the OUT Data Phase of a control transaction needs to: 1. Load the data to be sent into the endpoint 0 FIFO. 2.

  • Page 48: Out Data Phase Flow Chart

    USB Controller Host and Peripheral Modes Operation If NAK_TIMEOUT is set, it means that the controller has received a NAK response to each attempt to send the OUT token, for longer than the time set in the HOST_NAKLIMIT0 register. The controller can then be directed either to continue trying this transaction (until it times out again) by clearing the NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit.

  • Page 49: Completion Of Setup Or Out Data Phase Flow Chart

    www.ti.com 3.2.1.4 IN Status Phase (following SETUP Phase or OUT Data Phase) For the IN Status Phase of a Control Transaction needs to: 1. Set the STATUSPKT and REQPKT bits of HOST_CSR0 (bit 6 and bit 5, respectively). 2. Wait while the controller sends an IN token and receives a response from the USB peripheral device. Figure 12.
  • Page 50 USB Controller Host and Peripheral Modes Operation 3. When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0) has been set.

  • Page 51: Completion Of In Data Phase Flow Chart

    www.ti.com Figure 13. Completion of IN Data Phase Flow Chart NAK limit reached Error count cleared NAK Timeout set Endpoint halted Interrupt generated SPRUGH3 – November 2008 Submit Documentation Feedback USB Controller Host and Peripheral Modes Operation Completion of IN data phase TxPktRdy and StatusPkt both set...
  • Page 52 USB Controller Host and Peripheral Modes Operation 3.2.2 Bulk Transactions 3.2.2.1 Host Mode: Bulk IN Transactions A Bulk IN transaction may be used to transfer non-periodic data from the external USB peripheral to the host. The following optional features are available for use with an Rx endpoint used in host mode to receive the data: Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception from the host.
  • Page 53 www.ti.com 3.2.2.1.2 Operation When Bulk data is required from the USB peripheral device, the software should set the REQPKT bit in the corresponding HOST_RXCSR register (bit 5). The controller will then send an IN token to the selected peripheral endpoint and waits for data to be returned. If data is correctly received, RXPKTRDY bit of HOST_RXCSR (bit 0) is set.
  • Page 54 USB Controller Host and Peripheral Modes Operation The HOST_TXINTERVAL register needs to be written with the required value for the NAK limit (2 - 215 frames/microframes), or cleared to 0 if the NAK timeout feature is not required. The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for this endpoint).
  • Page 55 www.ti.com 3.2.4 Isochronous Transactions 3.2.4.1 Host Mode: Isochronous IN Transactions An Isochronous IN transaction is used to transfer periodic data from the USB peripheral to the host. The following optional features are available for use with an Rx endpoint used in Host mode to receive this data: Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception from the host.
  • Page 56 USB Controller Host and Peripheral Modes Operation FIFO unload requests will probably be irregular. If the data sink for the endpoint is going to some external hardware, it may be better to minimize the requirement for additional buffering by waiting until the end of each frame before unloading the FIFO.

  • Page 57: Dma Operation

    www.ti.com 3.2.4.2.2 Operation The operation starts when the software writes to the FIFO and sets TXPKTRDY bit of HOST_TXCSR (bit 0). This triggers the controller to send an OUT token followed by the first data packet from the FIFO. An interrupt is generated whenever a packet is sent and the software may use this interrupt to load the next packet into the FIFO and set the TXPKTRDY bit in the HOST_TXCSR register (bit 0) in the same way as for a Bulk Tx endpoint.

  • Page 58: Transmit Buffer Descriptor Word 2

    USB Controller Host and Peripheral Modes Operation End of queue (EOQ) (only valid on EOP) Packet Length (only valid with SOP) Transmit buffer descriptors contain 16 bytes (4 words) and must begin on 16-byte aligned addresses. Transmit buffer descriptors may be linked together to form packets. Buffer descriptor SOP and EOP bits are used to delimit packets.
  • Page 59 www.ti.com Table 9. Transmit Buffer Descriptor Word 3 (continued) Bits Name Value 27:24 Reserved Zero Byte 22:16 Reserved 15:0 Packet Length Four different cases are possible for the number of buffers in a DMA packet: 1. Buffer Descriptor contains Start of Packet field and End of Packet field (1 buffer in DMA packet). 2.

  • Page 60: Tx Queue Flow Chart

    USB Controller Host and Peripheral Modes Operation 3.3.1.4 Transmit Queue Figure 14 shows a Tx queue. Tx queue provide a logical queue of DMA packets for transmission through a channel. Each channel has one dedicated Tx queues. The queue has one associated Tx Queue Head Descriptor Pointer and one associated Tx Completion Pointer container in the channel Tx DMA state.
  • Page 61 www.ti.com clear the Ownership bit in the DMA packet’s SOP buffer descriptor and issue an interrupt to the processor by writing the DMA packet’s last buffer descriptor address to the queue’s Tx DMA State Completion Pointer (TCPPICOMPPTR register). When the last packet in a queue has been transmitted, the DMA controller sets the End Of Queue bit in the EOP buffer descriptor, clears the Ownership bit in the SOP Descriptor, zeroes the appropriate DMA state head descriptor pointer, and then issues a Tx interrupt to the host by writing address of the last buffer descriptor processed by the DMA controller to the queue’s...
  • Page 62 USB Controller Host and Peripheral Modes Operation RNDIS Mode Setup The setup of RNDIS mode DMA is similar to the default Transparent Mode as mentioned in the previous section. The following steps need to be taken for setting up RNDIS mode Tx DMA: After reset the software must write zeroes to all Tx DMA State registers (TCPPIDMASTATEW0, TCPPIDMASTATEW1, TCPPIDMASTATEW5).

  • Page 63: Receive Buffer Descriptor Word 2

    www.ti.com 3.3.2.2 CPPI Receive Buffer Descriptor Rx buffer descriptors provide information about a single corresponding Rx data buffer. Every Rx buffer has a single Rx buffer descriptor that stores the following information: Pointer to the data buffer Pointer to the next buffer descriptor in the queue Buffer length and offset to the first valid byte of buffer data Start of DMA packet (SOP) indicator End of DMA packet (EOP) indicator...

  • Page 64: Receive Buffer Descriptor Word

    USB Controller Host and Peripheral Modes Operation Field Value Description Ownership 27:24 Reserved Zero Byte 22:16 Reserved 15:0 Packet Length Four different cases are possible for the number of buffers in a DMA packet: 1. Buffer Descriptor contains Start of Packet field and End of Packet field (1 buffer in DMA packet) 2.

  • Page 65: Rx Queue Flow Chart

    www.ti.com 3.3.2.4 Receive Queue Figure 15 shows an Rx Queue. Rx queue provide a logical queue of processor memory space for DMA packets to be received from DMA controller channel. Each channel has single Rx queue. There are no multiple queue as in transmit channels. Each queue has one associated Rx Queue Head Descriptor Pointer and one associated Rx Completion Pointer contained in the channel Rx DMA State.
  • Page 66 USB Controller Host and Peripheral Modes Operation The software enables packet reception on a given channel by writing the address of the first buffer descriptor in the queue (nonzero value) to the channel’s head descriptor pointer (RCCPIDMASTATEW1) in the channel’s Rx DMA state. When packet reception begins on a given channel, the DMA controller fills each Rx buffer with data in order starting with the first buffer and proceeding through the Rx queue.
  • Page 67 www.ti.com 3.3.2.6 Receive Abort Handling The DMA controller sets ‘Rx Abort’ bit used to identify Rx packets which were aborted due to lack of buffers. Software must take care to inspect any Rx SOP packet for this bit and ignore all the buffers in that packet as the packet is incomplete.

  • Page 68: Interrupt Handling

    USB Controller Host and Peripheral Modes Operation If RXn_AUTOREQ (where n is the channel number) of AUTOREQ register is set with binary 11, IN tokens will be generated and sent to the target USB peripheral device even after the End Of DMA Packet is reached.
  • Page 69 www.ti.com Table 15. USB Interrupt Conditions (continued) Interrupt USB[3] USB[2] USB[1] USB[0] SPRUGH3 – November 2008 Submit Documentation Feedback USB Controller Host and Peripheral Modes Operation Description SOF started Reset Signaling detected (In Peripheral Mode) Babble detected (In Host Mode) Resume signaling detected Suspend Signaling detected Universal Serial Bus (USB) Controller...

  • Page 70: Test Modes

    USB Controller Host and Peripheral Modes Operation 3.4.1 USB Core Interrupts There are two methods available for software to access USB core interrupts, selectable by the UINT bit of CTRLR. The UINT bit cleared to 0 selects the PDR 2.0 compliant register set (INTSRCR, INTSETR, INTCLRR, INTMSKR, INTMSKSETR, INTMSKCLRR, INTMASKEDR).
  • Page 71 www.ti.com 3.5.1 TEST_SE0_NAK To enter the Test_SE0_NAK test mode, the software should set the Test_SE0-NAK bit by writing 0x01 to the TestMode register. The controller will then go into a mode in which it responds to any valid IN token with a NAK.
  • Page 72 USB Controller Host and Peripheral Modes Operation 3.5.4 TEST_PACKET To execute the Test_Packet, the software should: 1. Start a session (if the core is being used in Host mode). 2. Write the standard test packet (shown below) to the Endpoint 0 FIFO. 3.
  • Page 73 www.ti.com 3.5.6 FORCE_HOST The Force Host test mode enables the user to instruct the core to operate in Host mode, regardless of whether it is actually connected to any peripheral, i.e., the state of the CID input and the LINESTATE and HOSTDISCON signals are ignored.

  • Page 74: Reset Considerations

    USB Controller Host and Peripheral Modes Operation Reset Considerations The USB controller has two reset sources: hardware reset and the soft reset (RESET bit in CTRLR register). 3.6.1 Software Reset Considerations When the RESET bit in CTRLR is set, all the USB controller registers and DMA operations are reset. The bit is cleared automatically.

  • Page 75: Registers

    www.ti.com Registers Table 16 lists the memory-mapped registers for the universal serial bus (USB). See the device-specific data manual for the memory address of these registers. The base address is 01C6 4000h. Note: In some cases, a single register address can have different names or meanings depending on the mode (host/peripheral) or the setting of the index register.
  • Page 76 Registers Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym 124h RCPPIDMASTATEW1 128h RCPPIDMASTATEW2 12Ch RCPPIDMASTATEW3 130h RCPPIDMASTATEW4 134h RCPPIDMASTATEW5 138h RCPPIDMASTATEW6 13Ch RCPPICOMPPTR 140h TCPPIDMASTATEW0 144h TCPPIDMASTATEW1 148h TCPPIDMASTATEW2 14Ch TCPPIDMASTATEW3 150h TCPPIDMASTATEW4 154h TCPPIDMASTATEW5 15Ch TCPPICOMPPTR 160h RCPPIDMASTATEW0 164h RCPPIDMASTATEW1...
  • Page 77 www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym 1DCh TCPPICOMPPTR 1E0h RCPPIDMASTATEW0 1E4h RCPPIDMASTATEW1 1E8h RCPPIDMASTATEW2 1ECh RCPPIDMASTATEW3 1F0h RCPPIDMASTATEW4 1F4h RCPPIDMASTATEW5 1F8h RCPPIDMASTATEW6 1FCh RCPPICOMPPTR 400h FADDR 401h POWER 402h INTRTX 404h INTRRX 406h INTRTXE 408h INTRRXE 40Ah INTRUSB...
  • Page 78 Registers Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym 41Bh HOST_NAKLIMIT0 HOST_TXINTERVAL 41Ch HOST_RXTYPE 41Dh HOST_RXINTERVAL 41Fh CONFIGDATA 420h FIFO0 424h FIFO1 428h FIFO2 42Ch FIFO3 430h FIFO4 460h DEVCTL 462h TXFIFOSZ 463h RXFIFOSZ 464h TXFIFOADDR 466h RXFIFOADDR Target Endpoint 0 Control Registers, Valid Only in Host Mode 480h TXFUNCADDR...
  • Page 79 www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Target Endpoint 1 Control Registers, Valid Only in Host Mode 488h TXFUNCADDR 48Ah TXHUBADDR 48Bh TXHUBPORT 48Ch RXFUNCADDR 48Eh RXHUBADDR 48Fh RXHUBPORT Target Endpoint 2 Control Registers, Valid Only in Host Mode 490h TXFUNCADDR 492h...
  • Page 80 Registers Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym 49Eh RXHUBADDR 49Fh RXHUBPORT Target Endpoint 4 Control Registers, Valid Only in Host Mode 4A0h TXFUNCADDR 4A2h TXHUBADDR 4A3h TXHUBPORT 4A4h RXFUNCADDR 4A6h RXHUBADDR 4A7h RXHUBPORT 502h PERI_CSR0 HOST_CSR0 508h COUNT0 50Ah...
  • Page 81 www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym 51Dh HOST_RXINTERVAL 520h TXMAXP 522h PERI_TXCSR HOST_TXCSR 524h RXMAXP 526h PERI_RXCSR HOST_RXCSR 528h RXCOUNT 52Ah HOST_TXTYPE 52Bh HOST_TXINTERVAL 52Ch HOST_RXTYPE 52Dh HOST_RXINTERVAL 530h TXMAXP 532h PERI_TXCSR HOST_TXCSR 534h RXMAXP 536h PERI_RXCSR HOST_RXCSR...

  • Page 82: Control Register (Ctrlr)

    Registers Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym 546h PERI_RXCSR HOST_RXCSR 548h RXCOUNT 54Ah HOST_TXTYPE 54Bh HOST_TXINTERVAL 54Ch HOST_RXTYPE 54Dh HOST_RXINTERVAL Control Register (CTRLR) The Control Register (CTRLR) is shown in Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17.

  • Page 83: Status Register (Statr)

    www.ti.com Status Register (STATR) The Status Register (STATR) is shown in LEGEND: R = Read only; -n = value after reset Table 18. Status Register (STATR) Field Descriptions Field Value Description 31-1 Reserved Reserved DRVVBUS Current DRVVBUS value. DRVVBUS value is logic 0 DRVVBUS value is logic 1 RNDIS Register (RNDISR) The RNDIS Register (RNDISR) is shown in...

  • Page 84: Auto Request Register (Autoreq)

    Registers Auto Request Register (AUTOREQ) The Auto Request Register (AUTOREQ) is shown in Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20. Auto Request Register (AUTOREQ) Field Descriptions Field Value Description 31-8 Reserved Reserved 0-3h RX endpoint 4 Auto Req enable.

  • Page 85: Usb Interrupt Source Register (Intsrcr)

    www.ti.com USB Interrupt Source Register (INTSRCR) The USB Interrupt Source Register (INTSRCR) is shown in Figure 20. USB Interrupt Source Register (INTSRCR) Reserved Reserved LEGEND: R = Read only; -n = value after reset Table 21. USB Interrupt Source Register (INTSRCR) Field Descriptions Field Value Description...

  • Page 86: Usb Interrupt Source Set Register (Intsetr)

    Registers USB Interrupt Source Set Register (INTSETR) The USB Interrupt Source Set Register (INTSETR) is shown in Figure 21. USB Interrupt Source Set Register (INTSETR) Reserved Reserved LEGEND: R = Read only; W = Write only; -n = value after reset Table 22.

  • Page 87: Usb Interrupt Source Clear Register (Intclrr)

    www.ti.com USB Interrupt Source Clear Register (INTCLRR) The USB Interrupt Source Clear Register (INTCLRR) is shown in Figure 22. USB Interrupt Source Clear Register (INTCLRR) Reserved Reserved LEGEND: R = Read only; W = Write only; -n = value after reset Table 23.

  • Page 88: Usb Interrupt Mask Register (Intmskr)

    Registers USB Interrupt Mask Register (INTMSKR) The USB Interrupt Mask Register (INTMSKR) is shown in Figure 23. USB Interrupt Mask Register (INTMSKR) Reserved Reserved LEGEND: R = Read only; -n = value after reset Table 24. USB Interrupt Mask Register (INTMSKR) Field Descriptions Field Value Description...

  • Page 89: Usb Interrupt Mask Set Register (Intmsksetr)

    www.ti.com USB Interrupt Mask Set Register (INTMSKSETR) The USB Interrupt Mask Set Register (INTMSKSETR) is shown in Figure 24. USB Interrupt Mask Set Register (INTMSKSETR) Reserved Reserved LEGEND: R = Read only; W = Write only; -n = value after reset Table 25.

  • Page 90: Usb Interrupt Mask Clear Register (Intmskclrr)

    Registers 4.10 USB Interrupt Mask Clear Register (INTMSKCLRR) The USB Interrupt Mask Clear Register (INTMSKCLRR) is shown in Figure 25. USB Interrupt Mask Clear Register (INTMSKCLRR) Reserved Reserved LEGEND: R = Read only; W = Write only; -n = value after reset Table 26.

  • Page 91: Usb Interrupt Source Masked Register (Intmaskedr)

    www.ti.com 4.11 USB Interrupt Source Masked Register (INTMASKEDR) The USB Interrupt Source Masked Register (INTMASKEDR) is shown in Table Figure 26. USB Interrupt Source Masked Register (INTMASKEDR) Reserved Reserved LEGEND: R = Read only; -n = value after reset Table 27. USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions Field Value Description...

  • Page 92: Usb End Of Interrupt Register (Eoir)

    Registers 4.12 USB End of Interrupt Register (EOIR) The USB End of Interrupt Register (EOIR) is shown in Figure 27. USB End of Interrupt Register (EOIR) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28.

  • Page 93: Transmit Cppi Control Register (Tcppicr)

    www.ti.com 4.14 Transmit CPPI Control Register (TCPPICR) The Transmit CPPI Control Register (TCPPICR) is shown in Figure 29. Transmit CPPI Control Register (TCPPICR) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30. Transmit CPPI Control Register (TCPPICR) Field Descriptions Field Value Description...

  • Page 94: Cppi Dma End Of Interrupt Register (Cppieoir)

    Registers 4.16 CPPI DMA End of Interrupt Register (CPPIEOIR) Note: This register was previously named TCPPIEOIR, and that name will continue to exist in the CSL for backward compatibility. The CPPI DMA End of Interrupt Register (CPPIEOIR) is shown in Figure 31.

  • Page 95: Transmit Cppi Masked Status Register (Tcppimsksr)

    www.ti.com 4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) The Transmit CPPI Masked Status Register (TCPPIMSKSR) is shown in Table Figure 32. Transmit CPPI Masked Status Register (TCPPIMSKSR) LEGEND: R = Read only; -n = value after reset Table 33. Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions Field 31-4 Reserved...

  • Page 96: Transmit Cppi Interrupt Enable Set Register (Tcppiiensetr)

    Registers 4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) The Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) is shown in Table Figure 34. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 35.

  • Page 97: Receive Cppi Control Register (Rcppicr)

    www.ti.com 4.21 Receive CPPI Control Register (RCPPICR) The Receive CPPI Control Register (RCPPICR) is shown in Figure 36. Receive CPPI Control Register (RCPPICR) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 37. Receive CPPI Control Register (RCPPICR) Field Descriptions Field Value Description...

  • Page 98: Receive Cppi Raw Status Register (Rcppirawsr)

    Registers 4.23 Receive CPPI Raw Status Register (RCPPIRAWSR) The Receive CPPI Raw Status Register (RCPPIRAWSR) is shown in Table Figure 38. Receive CPPI Raw Status Register (RCPPIRAWSR) LEGEND: R = Read only; -n = value after reset Table 39. Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions Field Value 31-4...

  • Page 99: Receive Cppi Interrupt Enable Clear Register (Rcppiienclrr)

    www.ti.com 4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) The Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) is shown in Table Figure 40. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 41.

  • Page 100: Receive Buffer Count 1 Register (Rbufcnt1)

    Registers 4.27 Receive Buffer Count 1 Register (RBUFCNT1) The Receive Buffer Count 1 Register (RBUFCNT1) is shown in Figure 42. Receive Buffer Count 1 Register (RBUFCNT1) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 43. Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions Field Value Description...

  • Page 101: Receive Buffer Count 3 Register (Rbufcnt3)

    www.ti.com 4.29 Receive Buffer Count 3 Register (RBUFCNT3) The Receive Buffer Count 3 Register (RBUFCNT3) is shown in Figure 44. Receive Buffer Count 3 Register (RBUFCNT3) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 45. Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions Field Value Description...

  • Page 102: Transmit Cppi Dma State Word 1 (Tcppidmastatew1)

    Registers 4.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) The Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) is shown in Table Figure 46. Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) SOP_DESCRIPTOR_PTR LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 47.

  • Page 103: Transmit Cppi Dma State Word 3 (Tcppidmastatew3)

    www.ti.com Table 48. Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions (continued) Field Reserved 4.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) The Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) is shown in Table Figure 48. Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) LEGEND: R/W = Read/Write;...

  • Page 104: Transmit Cppi Dma State Word 5 (Tcppidmastatew5)

    Registers Table 50. Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions (continued) Field 15-0 CURR_BUFFER_LENGTH 4.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) The Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) is shown in Table Figure 50. Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) LEGEND: R/W = Read/Write;...

  • Page 105: Receive Cppi Dma State Word 0 (Rcppidmastatew0)

    www.ti.com Table 52. Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions Field Value 31-2 DESC_ADDR 0-3FFF FFFFh Reserved WRBK_MODE 4.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) The Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) is shown in Table Figure 52. Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Reserved R/W-0 LEGEND: R/W = Read/Write;...

  • Page 106: Receive Cppi Dma State Word 1 (Rcppidmastatew1)

    Registers Figure 53. Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 54. Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions Field Value 31-2 RXQ_HEAD_PTR 0-1FFF FFFFh Reserved Universal Serial Bus (USB) Controller RXQ_HEAD_PTR...

  • Page 107: Receive Cppi Dma State Word 2 (Rcppidmastatew2)

    www.ti.com 4.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) The Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) is shown in Table Figure 54. Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) SOP_DESCRIPTOR_PTR LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 55.
  • Page 108 Registers www.ti.com Universal Serial Bus (USB) Controller SPRUGH3 – November 2008 Submit Documentation Feedback...

  • Page 109: Receive Cppi Dma State Word 4 (Rcppidmastatew4)

    www.ti.com 4.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) The Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) is shown in Table Figure 56. Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) LEGEND: R/W = Read/Write; -n = value after reset Table 57. Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Field Descriptions Field Value 31-0...

  • Page 110: Receive Cppi Dma State Word 6 (Rcppidmastatew6)

    Registers 4.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) The Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) is shown in Table Figure 58. Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) LEGEND: R/W = Read/Write; -n = value after reset Table 59. Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) Field Descriptions Field 31-16 SOP_BUFFER_BYTECNT 15-0...

  • Page 111: Function Address Register (Faddr)

    www.ti.com Table 60. Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions (continued) Field Value RDBK_MODE 4.45 Function Address Register (FADDR) The Function Address Register (FADDR) is shown in Reserved LEGEND: R/W = Read/Write; -n = value after reset Table 61. Function Address Register (FADDR) Field Descriptions Field Value Description...

  • Page 112: Interrupt Register For Endpoint 0 Plus Transmit Endpoints 1 To 4 (Intrtx)

    Registers Table 62. Power Management Register (POWER) Field Descriptions (continued) Field Value Description RESET This bit is set when Reset signaling is present on the bus. Note: This bit is Read/Write in Host Mode, but read-only in Peripheral Mode. RESUME Set to generate Resume signaling when the controller is in Suspend mode.

  • Page 113: Interrupt Enable Register For Intrrx (Intrrxe)

    www.ti.com Figure 63. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Reserved LEGEND: R = Read only; -n = value after reset Table 64. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions Field Value Description 15-5 Reserved Reserved EP4RX...

  • Page 114: Interrupt Enable Register For Intrrx (Intrrxe)

    Registers Figure 65. Interrupt Enable Register for INTRRX (INTRRXE) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 66. Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions Field Value Description 15-5 Reserved Reserved EP4RX 1/0 = Receive Endpoint 4 interrupt enable/disable EP3RX 1/0 = Receive Endpoint 3 interrupt enable/disable...

  • Page 115: Interrupt Register For Common Usb Interrupts (Intrusb)

    www.ti.com 4.51 Interrupt Register for Common USB Interrupts (INTRUSB) The Interrupt Register for Common USB Interrupts (INTRUSB) is shown in Table 67. Reading this register causes all bits to be cleared. Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the INTSRCR register instead.

  • Page 116: Interrupt Enable Register For Intrusb (Intrusbe)

    Registers 4.52 Interrupt Enable Register for INTRUSB (INTRUSBE) The Interrupt Enable Register for INTRUSB (INTRUSBE) is shown in Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the INTMSKSETR/INTMSKCLRR registers instead. Figure 67.

  • Page 117: Frame Number Register (Frame)

    www.ti.com 4.53 Frame Number Register (FRAME) The Frame Number Register (FRAME) is shown in Reserved LEGEND: R = Read only; -n = value after reset Table 69. Frame Number Register (FRAME) Field Descriptions Field Value 15-11 Reserved 10-0 FRAMENUMBER 0-7FFh Last received frame number 4.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) The Index Register for Selecting the Endpoint Status and Control Registers (INDEX) is shown in and described in...

  • Page 118: Register To Enable The Usb 2.0 Test Modes (Testmode)

    Registers 4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE) The Register to Enable the USB 2.0 Test Modes (TESTMODE) is shown in Table Figure 70. Register to Enable the USB 2.0 Test Modes (TESTMODE) FORCE_HOST FIFO_ACCESS FORCE_FS R/W-0 R/W-0 LEGEND: R/W = Read/Write;...

  • Page 119: Maximum Packet Size For Peripheral/Host Transmit Endpoint (Txmaxp)

    www.ti.com 4.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) The Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) is shown in described in Table Figure 71. Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 72.

  • Page 120: Control Status Register For Endpoint 0 In Peripheral Mode (Peri_Csr0)

    Registers 4.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) The Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) is shown in described in Table Figure 72. Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) SERV_SETUPEND SERV_RXPKTRDY SENDSTALL...

  • Page 121: Control Status Register For Endpoint 0 In Host Mode (Host_Csr0) Field Descriptions

    www.ti.com 4.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) The Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) is shown in described in Table Figure 73. Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Reserved NAK_TIMEOUT STATUSPKT...

  • Page 122: Control Status Register For Peripheral Transmit Endpoint (Peri_Txcsr)

    Registers 4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) The Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) is shown in described in Table Figure 74. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Reserved MODE R/W-0 R/W-0 CLRDATATOG SENTSTALL SENDSTALL R/W-0...

  • Page 123: Control Status Register For Host Transmit Endpoint (Host_Txcsr) Field Descriptions

    www.ti.com 4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) The Control Status Register for Host Transmit Endpoint (HOST_TXCSR) is shown in described in Table Figure 75. Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Reserved MODE R/W-0 NAK_TIMEOUT CLRDATATOG RXSTALL R/W-0 LEGEND: R/W = Read/Write;...

  • Page 124: Maximum Packet Size For Peripheral Host Receive Endpoint (Rxmaxp)

    Registers 4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) The Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) is shown in described in Table Figure 76. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 77.

  • Page 125: Control Status Register For Peripheral Receive Endpoint (Peri_Rxcsr)

    www.ti.com 4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) The Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) is shown in described in Table Figure 77. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Reserved DMAEN R/W-0 R/W-0 CLRDATATOG SENTSTALL SENDSTALL R/W-0...

  • Page 126: Control Status Register For Host Receive Endpoint (Host_Rxcsr) Field Descriptions

    Registers 4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR) The Control Status Register for Host Receive Endpoint (HOST_RXCSR) is shown in described in Table Figure 78. Control Status Register for Host Receive Endpoint (HOST_RXCSR) Reserved DMAEN R/W-0 CLRDATATOG RXSTALL REQPKT R/W-0 R/W-0...
  • Page 127 Registers www.ti.com SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller Submit Documentation Feedback...

  • Page 128: Count 0 Register (Count0)

    Registers 4.64 Count 0 Register (COUNT0) The Count 0 Register (COUNT0) is shown in Reserved LEGEND: R = Read only; -n = value after reset Table 80. Count 0 Register (COUNT0) Field Descriptions Field Value Description 15-7 Reserved Reserved EP0RXCOUNT 0-7Fh Indicates the number of received data bytes in the Endpoint 0 FIFO.

  • Page 129: Type Register (Host Mode Only) (Host_Type0) Field Descriptions

    www.ti.com 4.66 Type Register (Host mode only) (HOST_TYPE0) The Type Register (Host mode only) (HOST_TYPE0) is shown in Figure 81. Type Register (Host mode only) (HOST_TYPE0) SPEED R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 82.

  • Page 130: Transmit Interval Register (Host Mode Only) (Host_Txinterval)

    Registers 4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) The NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) is shown in Table Figure 83. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 84.

  • Page 131: Receive Interval Register (Host Mode Only) (Host_Rxinterval)

    www.ti.com 4.70 Receive Type Register (Host mode only) (HOST_RXTYPE) The Receive Type Register (Host mode only) (HOST_RXTYPE) is shown in Table Figure 85. Receive Type Register (Host mode only) (HOST_RXTYPE) SPEED R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 86.

  • Page 132: Configuration Data Register (Configdata)

    Registers Table 87. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions Field Value POLINTVL_NAKLIMIT 0-FFh 4.72 Configuration Data Register (CONFIGDATA) The configuration data register (CONFIGDATA) is shown in Figure 87. Configuration Data Register (CONFIGDATA) MPRXE MPTXE BIGENDIAN LEGEND: R = Read only; -n = value after reset Table 88.
  • Page 133 Registers www.ti.com SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller Submit Documentation Feedback...

  • Page 134: Transmit And Receive Fifo Register For Endpoint 0 (Fifo0)

    Registers 4.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) The Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) is shown in Table Figure 88. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) LEGEND: R/W = Read/Write; -n = value after reset Table 89.

  • Page 135: Transmit And Receive Fifo Register For Endpoint 1 (Fifo1)

    www.ti.com 4.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) The Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) is shown in Table Figure 89. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) LEGEND: R/W = Read/Write; -n = value after reset Table 90.

  • Page 136: Transmit And Receive Fifo Register For Endpoint 3 (Fifo3)

    Registers 4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) The Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) is shown in Table Figure 91. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) LEGEND: R/W = Read/Write; -n = value after reset Table 92.

  • Page 137: Otg Device Control Register (Devctl)

    www.ti.com 4.78 OTG Device Control Register (DEVCTL) The OTG Device Control Register (DEVCTL) is shown in Figure 93. OTG Device Control Register (DEVCTL) BDEVICE FSDEV LSDEV LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 94. OTG Device Control Register (DEVCTL) Field Descriptions Field Value Description...

  • Page 138: Transmit Endpoint Fifo Size (Txfifosz)

    Registers 4.79 Transmit Endpoint FIFO Size (TXFIFOSZ) Section 2.5 describes dynamically setting endpoint FIFO sizes. The Transmit Endpoint FIFO Size (TXFIFOSZ) is shown in Figure 94. Transmit Endpoint FIFO Size (TXFIFOSZ) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 95.

  • Page 139: Transmit Endpoint Fifo Address (Txfifoaddr)

    www.ti.com 4.81 Transmit Endpoint FIFO Address (TXFIFOADDR) Section 2.5 describes dynamically setting endpoint FIFO sizes. The Transmit Endpoint FIFO Address (TXFIFOADDR) is shown in Figure 96. Transmit Endpoint FIFO Address (TXFIFOADDR) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 97.

  • Page 140: Transmit Function Address (Txfuncaddr)

    Registers 4.83 Transmit Function Address (TXFUNCADDR) The Transmit Function Address (TXFUNCADDR) is shown in Figure 98. Transmit Function Address (TXFUNCADDR) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 99. Transmit Function Address (TXFUNCADDR) Field Descriptions Field Value Description...

  • Page 141: Receive Function Address (Rxfuncaddr)

    www.ti.com 4.86 Receive Function Address (RXFUNCADDR) The Receive Function Address (RXFUNCADDR) is shown in Figure 101. Receive Function Address (RXFUNCADDR) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 102. Receive Function Address (RXFUNCADDR) Field Descriptions Field Value Description...
  • Page 142 Registers www.ti.com Universal Serial Bus (USB) Controller SPRUGH3 – November 2008 Submit Documentation Feedback...

  • Page 143: Appendix A Revision History

    www.ti.com Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Section 1 Added note. Section 1.3 Added section. Section 2.4 Changed section. Section 3.1.1 Renamed section. Section 3.1.2.1 Renamed section. Section 3.1.2.2 Renamed section.

  • Page 144: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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