GE Solar 8000M/i Service Manual page 34

Video system
2-18
Equipment overview: Theory of operation
FPGA logic chip – The Processor PCB has one (1) Field Programmable
Gate Array logic chip on the board to provide the PCI host bridge
interface, the TRAM-NET strobe processing, the M-port support and a
revision port. The FPGA used is an Altera 6016 FLEX FPGA. The FPGA
is configured at power up by the Boot Code startup software loading the
FPGA configuring data into the FPGA. Therefore the FPGA does not
contain any functionality that is needed to allow the MPC860 to access
and execute Boot Code or any other necessary facilities needed to get the
processor PCB initialized at startup. In addition, any signal lines that
the FPGA drives must be able to accommodate the fact that at power up
the FPGA lines are high impedance until the FPGA is programmed.
NOTE
The FPGA must be 5V I/O tolerant since it is interfacing the older
+5V technology parts such as the TRAM-NET Hub.
The video system consists of one video accelerator and two duplicate sets
of CRT and flat panel buffers. A maximum of two analog and two digital
flat panel displays can be used.
A 65.00 MHz clock oscillator is used to drive the video system. The
MPC860 accesses the video systems over the PCI Bus using the Host
Bridge implementation within the FPGA.
Video system components
The video system has a video graphics chip, some discretes and
connectors for VGA (RGB) and DFP (Digital Flat Panel) video displays as
well as a RS-232 serial port to provide for a Touchscreen input.
Video graphics chip – The video graphics accelerator chip has the
following facilities:
4 Mbytes of internal memory
A bandwidth of 800 Mbytes/second minimum
RAMDAC for direct VGA/RGB output
Flat Panel Drive (using SiI164 components)
Programmable Ports Pins
VGA video output – The RGB output from the graphics accelerator is
used to generate the video signals output on the 15 pin VGA video
connectors.
DFP video output – Flat Panel drive signals from the video accelerator
are interfaced to a Silicon Image SiI164's.The SiI164's convert signals to
transition Minimized Differential Signaling (TMDS) levels before
connection to the 20 pin MDR DFP connectors.
RS-232 serial ports
The RS-232 serial ports provide the interface to the iPanel computer
(RS-232 1) and serial communication devices such as a touchscreen
display. See the Communication System for detailed discussion.
Solar 8000M/i patient monitor 2026265-075C