Memories; Dma (Direct Memory Access); Lcd (Liquid Crystal Display) - STMicroelectronics STM32L100RC Manual

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STM32L100RC
3.7

Memories

The STM32L100RC device has the following features:
•
16 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
–
–
The options bytes are used to write-protect or read-out protect the memory (with 4 KB
granularity) and/or readout-protect the whole memory with the following options:
–
–
–
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8

DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I
DAC and ADC.
3.9

LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 32 segment terminals to drive up to 320224
pixels.
•
Internal step-up converter to guarantee functionality and contrast control irrespective of
V
DD
the voltage to the LCD
•
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
•
Supports static, 1/2, 1/3 and 1/4 bias
•
Phase inversion to reduce power consumption and EMI
•
Up to 8 pixels can be programmed to blink
•
Unneeded segments and common pins can be used as general I/O pins
•
LCD RAM can be updated at any time owing to a double-buffer
•
The LCD controller can operate in Stop mode
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128 Kbytes of embedded Flash program memory
4 Kbytes of data EEPROM
Options bytes
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
. This converter can be deactivated, in which case the V
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2
C, USART, general-purpose timers,
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pin is used to provide
LCD
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