Voltage Regulator; Boot Modes - STMicroelectronics STM32L100RC Manual

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STM32L100RC
power ramp-up should guarantee that 1.65 V is reached on V
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
V is below a specified threshold, V
DD
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for a device with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
V /V
DD DDA
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
V /V
DD DDA
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3

Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR) and power down.
•
MR is used in Run mode (nominal regulation)
•
LPR is used in the Low-power run, Low-power sleep and Stop modes
•
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4

Boot modes

At startup, boot pins are used to select one of three boot options:
•
Boot from Flash memory
•
Boot from System memory
•
Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1 and USART2. See Application note "STM32 microcontroller system memory
boot mode" (AN2606) for details.
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power supply and compares it to the V
is higher than the V
PVD
DocID024995 Rev 4
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) in Stop mode. The device remains in reset mode when
or V , without the need for any external
POR/PDR BOR
threshold. This PVD offers 7 different
PVD
/V drops below the V
DD DDA
threshold. The interrupt service routine can then generate
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at least 1 ms after it exits
DD
threshold and/or when
PVD
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