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Lattice Semiconductor
Table 27. 10/100/1000 Ethernet PHY Connection Summary
Description
ETH_CLK_TO_MAC
ETH_COL
ETH_CRS
ETH_EGP0
ETH_EGP2
ETH_EGP4
ETH_EGP5
ETH_EGP6
ETH_EGP7
ETH_GTX_CLK
ETH_MAC_CLK_EN
ETH_MDC
ETH_MDIO
ETH_RESET_N
ETH_RX_CLK
ETH_RX_D0
ETH_RX_D1
ETH_RX_D2
ETH_RX_D3
ETH_RX_D4
ETH_RX_D5
ETH_RX_D6
ETH_RX_D7
ETH_RX_DV
ETH_RX_ER
ETH_TX_CLK
ETH_TX_D0
ETH_TX_D1
ETH_TX_D2
ETH_TX_D3
ETH_TX_D4
ETH_TX_D5
ETH_TX_D6
ETH_TX_D7
ETH_TX_EN
ETH_TX_ER
PCI Connection
The 124-pin PCI connector installed at the bottom-left corner of the board is used for 32-bit PCI. With this PCI con-
nector, PCI IP and proper LatticeXP2 FPGA design, the LatticeXP2 Advanced Evaluation board can be used in a
PCI slot on a PC motherboard. There are two sides to the PCI connector, component side (J11) and solder side
(J56). Refer to Tables 28 and 29 for a description of the PCI connections where the I/O direction is referenced to
the LatticeXP2 Advanced Evaluation Board.
LatticeXP2 I/O
G11
A17
B16
(low, install R91 to pull high)
G13
G14
D12
B14
A15
D15
G10
E15
E14
A16
B15
F14
D14
C16
C17
B17
A18
F13
G12
C14
E13
C15
D17
E18
C18
C19
A20
D19
D17
D18
A19
A21
19
LatticeXP2 Advanced
Evaluation Board User's Guide
sysIO Bank
1
1
1
--
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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