Lattice Semiconductor XP2 Advanced User Manual page 8

Lattice Semiconductor
Prototype Areas
For general purpose I/O testing or monitoring, numerous test points are provided for direct access. Some test
points are grouped together and arranged in a grid pattern according to their associated I/O bank and are labeled
with the pin locations on the silkscreen of the board. Other test point I/Os are brought out to IDC connectors J1 and
J10 with both source and end termination resistors available for high speed parallel signal transmission over ribbon
cable.
Differential Signal Connections
There are four pairs of SMA connectors and one RJ-45 connector connected directly to the LatticeXP2 differential
I/O pairs.
The eight SMA connectors are provided for clocks or general purpose, user-definable signals. The center pin is
wired to an I/O pin and the outer case is soldered to ground. Table 9 details to which I/O pin each SMA connector
is wired.
Table 9. SMA Connectors
Location
1
J12
J6
J13
J7
J14
J8
J15
J9
1. The SMA connector on J12 is shared with the on-board oscillator. When this SMA connector is used, the jumper on
J17 needs to be removed.
RJ-45 Connectors
There are two RJ-45 connectors, J5 and J43, on the evaluation board. J5 is a simple RJ-45 female connector pro-
vided for general-purpose differential interfacing to the LatticeXP2 device, while J43 is a full featured Ethernet PHY
connection with internal magnetics and spark gap. The connections for J5 are listed in Table 10. J43 is described in
more detail in the Ethernet section later in this user guide.
Table 10. J5 RJ-45 Connections
J1 Pin
1
2
3
6
4
5
7
8
Oscillator
The 3.3V oscillator socket (Y1) accepts both full-size and half-size oscillators and can route to different clock
inputs, depending on its position within the socket (see Figure 2). The board is shipped with an EPSON program-
mable oscillator programmed to 33.33MHz.
LatticeXP2 I/O Polarity
A2* Pair#0 P
B3 Pair#0 N
F7 Pair#1 P
G7 Pair#1 N
P4 Pair#2 P
P5 Pair#2 N
Y1 Pair#3 P
AA1 Pair#3 N
LatticeXP2 I/O Polarity
P2 Pair#0 P
P3 Pair#0 N
T1 Pair#1 P
U1 Pair#1 N
M4 Pair#2 P
M5 Pair#2 N
R5 Pair#3 P
P6 Pair#3 N
Evaluation Board User's Guide
sysIO Bank
0 PT4A/ULC_GPLLT_IN_A
0 PT4B/ULC_GPLLC_IN_A
0 PT5A/ULC_GPLLT_FB_A
0 PT5B/ULC_GPLLC_FB_A
6
6
6
6
SysIO Bank
6
6
6
6
6
6
6
6
8
LatticeXP2 Advanced
Description
PL37A
PL37B
PL35A
PL35B
Description
PL32A
PL32B
PL30A/LDQS30
PL30B
PL28A
PL28B
PL40A
PL40B