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Lattice Semiconductor
Table 28. PCI Connector Component Side
J11 Pin#
Signal
1
12V
2
TCK
3
GND
4
TDO
5
5V
6
5V
7
INTB#
8
INTD#
9
PRSNT1#
10
Reserved
11
PRSNT2#
14
Reserved
15
GND
16
CLK
17
GND
18
REQ#
19
+VIO
20
AD[31]
21
AD[29]
22
GND
23
AD[27]
24
AD[25]
25
+3.3V
26
C/BE#[3]
27
AD[23]
28
GND
29
AD[21]
30
AD[19]
31
+3.3V
32
AD[17]
33
C/BE#[2]
34
GND
35
IRDY#
36
+3.3V
37
DEVSEL#
38
GND
39
LOCK#
40
PERR#
41
+3.3V
42
SERR#
43
+3.3V
44
C/BE#[1]
45
AD[14]
46
GND
I/O
Vcc
12V voltage supply pin
-
PCI JTAG TCK signal
Vss
System ground
-
JTAG TDO signal
Vcc
5V voltage supply pin
Vcc
5V voltage supply pin
O
PCI INTB# signal
O
PCI INTD# signal
O
PCI PRSNT1# signal
-
Reserved
O
PCI PRSNT2# signal
-
Reserved
Vss
System ground
I
PCI system clock
Vss
System ground
O
PCI arbitration request signal
Vio
VIO voltage supply pin
I/O
PCI address and bit 31
I/O
PCI address and data bit 29
Vss
System ground
I/O
PCI address and data bit 27
I/O
PCI address and data bit 25
Vcc
3.3V voltage supply pin
I/O
PCI bus command, byte enable, bit 3
I/O
PCI address and data bit 23
Vss
System ground
I/O
PCI address and data bit 21
I/O
PCI address and data bit 19
Vcc
3.3V voltage supply pin
I/O
PCI address and data bit 17
I/O
PCI bus command, byte enable, bit 2
Vss
System ground
I/O
PCI initiator ready signal
Vcc
3.3V voltage supply pin
I/O
PCI device select
Vss
System ground
I/O
PCI lock signal
I/O
PCI parity error signal
Vcc
3.3V voltage supply pin
I/O
PCI system error signal
Vcc
3.3V voltage supply pin
I/O
PCI bus command, byte enable, bit 1
I/O
PCI address and data bit 14
Vss
System ground
20
Evaluation Board User's Guide
Description
LatticeXP2 Advanced
LatticeXP2 Connection
—
—
GND
—
—
—
—
—
—
—
—
—
GND
AB14
GND
W5
—
Y5
Y6
GND
AB6
AA7
+3.3V
Y8
W4
GND
W6
U8
+3.3V
W8
V9
GND
T10
+3.3V
T9
GND
-
V10
+3.3V
V11
+3.3V
T12
T13
GND
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