Table of Contents
Advertisement
Lattice Semiconductor
Table 23. Connections Between USB 1.1 Transceiver and LatticeXP2 (Continued)
Pin #
MAX3454EETE NCN2500MNR2 LatticeXP2 I/O
13
ENUM
14
Vbus
15
VL
16
NC
PS/2 Mouse
The PS/2 mouse connector (JP1) on this board connects the clock and data through the PCA9306 level translator
to the LatticeXP2. The clock and data are connected as described in Table 24.
Table 24. Connections Between PS/2 Mouse Connector and LatticeXP2
JP1 Pin #
1
5
RS-232
The RS-232 interface on this board includes a RS-232 interface chip (MAX3232), a 9-pin D-sub female connector
and four headers. This RS-232 interface can be configured to DCE or DTE by changing the jumper settings of J27,
J28, J29 and J30 headers. These headers are used to connect the MAX3232 to the D-sub connector. Installing
jumpers on Pin 1 and Pin 2 of these headers configures the RS-232 to DCE. Installing jumpers on Pin 2 and Pin 3
of these headers configures the RS-232 to DTE. The connections and functions of the signals between MAX3232
and LatticeXP2 stay the same for DCE and DTE configurations. These are listed in Table 25.
Table 25.
Connections Between MAX3232 and LatticeXP2
Signal Name
/CTS
RXD
TXD
/RTS
DDR2
The 200-pin SODIMM socket provides a built-in 32-bit interface to standard 1.8V DDR2 SDRAM memory modules
(PC2-5300). Lattice recommends the Kingston KVR533D284/512. However, other memories conforming to this
standard will also work. The required V
vided. Performance has been verified at above the 533Mbps data rate. Write mode dynamic ODT at the memory
modules is fully supported, while read mode ODT at the controller (FPGA) is approximated with external termina-
tions optimized for best performance. The connections between the connector pins and LatticeXP2 balls are shown
in Table 26.
Table 26. DDR2 Interface to SODIMM Socket
Description
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
Vobus
Vusb
Vcc
EN_RPU
Signal
LatticeXP2 I/O
DATA
CLOCK
MAX3232 Pin
LatticeXP2 I/O
9 (R2OUT)
12 (R1OUT)
11 (T1IN)
10 (T2IN)
and V
REF
TT
LatticeXP2 I/O
R21
R20
N17
N16
P19
R19
Evaluation Board User's Guide
—
Connect to J21 pin 2
—
Connect to USB connectors
—
Connect to 3.3V
—
Connect to J21 pin 2
Description
V5
PS/2 data signal, open drain
V4
PS/2 clock signal, open drain
LatticeXP2 Bank
C3
B2
B1
C2
voltages, as well as termination of each signal to V
sysIO Bank
3
3
3
3
3
3
16
LatticeXP2 Advanced
Description
LatticeXP2 I/O Type
7
Input
7
Input
7
Output
7
Output
J36
5
7
17
19
4
6
are pro-
TT
Advertisement
Table of Contents
