Lattice Semiconductor XP2 Advanced User Manual page 10

Lattice Semiconductor
Table 11. JTAG Programming Headers
Jumper on J49 (None on J45)
Pin J39 Function
1 Vcc (3.3V)
2 TDO of ispPAC-POWR1220AT8
3 TDI of ispPAC-POWR1220AT8
4 NC
5 NC
6 TMS of both chips
7 GND
8 TCK of ispPAC-POWR1220AT8
9 NC
10 NC
J49 and J45 control the functions of the two programming headers. When a jumper is installed on J49, the pro-
gramming header J39 is connected to the JTAG port of ispPAC-POWR1220AT8 and is used for programming the
ispPAC-POWR1220AT8 only; the programming header J40 is connected to the JTAG port of LatticeXP2 and is
used for programming the LatticeXP2 only.
When the jumper is moved from J49 to J45, the JTAG ports of the LatticeXP2 and ispPAC-POWR1220AT8 are
chained together. In this case, the programming header J40 is connected to the JTAG port of the LatticeXP2 first
and then chained with the JTAG port of ispPAC-POWR1220AT8. The programming header J39 should not be used
when the JTAG ports are chained together. During chained programming, the ispPAC-POWR1220AT8 device will
set the HVOUT1 signal (pin 86 of U17) tri-state until programming completes, so the enable for the 3.3V power for
the LatticeXP2 device will be interrupted during programming unless a jumper is installed at J52. After chained pro-
gramming of the ispPAC-POWR1220AT8, the jumper at J52 can be removed.
Additional instructions and recommendations for programming this board are provided in the Configuring/Program-
ming the Board section of this document.
Switches
There are two 8-position switches and six push-button switches for implementing basic static input functions.
Switches SW3, SW4, SW5, SW6, SW7 and SW10 are momentary switches. The pull-up resistors associated with
these switches are wired to 3.3V. Pushing the switches down produces a low (0), otherwise it produces a high (1).
The signals controlled by SW4, SW5, SW6, SW7 and SW10 are debounced by an MC14490 (U15) before connect-
ing to an LatticeXP2 I/O pin. Table 12 shows the control relationship between the switches, LatticeXP2 and ispPAC-
POWR1220AT8 I/O pins.
Table 12. Momentary Switches
Switch
SW3
SW4
SW5
SW6
SW7
SW10
1. SW3 signal is also connected (wire-AND) to position#1 of SW2. Therefore, when position#1 of SW2 is in the down position,
SW3 signal (POWR1220AT8 pin 97) will be low even when SW3 is not being pushed.
Separate Programming
J40 Function
Vcc (3.3V)
TDO of LatticeXP2
TDI of LatticeXP2
TMS of both chips
TCK of LatticeXP2
DONE of LatticeXP2
INITN of LatticeXP2
Connection
Pin 97 of ispPAC-POWR1220AT8*
J6 of LatticeXP2 (PROGRAMN)
E12 of LatticeXP2 (GSRN)
W18 of LatticeXP2
W17 of LatticeXP2
U7 of LatticeXP2
TDO of ispPAC-POWR1220AT8
TDI of LatticeXP2
NC
NC
TMS of both chips
GND
TCK of both chips
User-Definable
10
LatticeXP2 Advanced
Evaluation Board User's Guide
Chained Programming
Jumper on J45 (None on J49)
J39 Function
Vcc (3.3V)
NC
NC
GND
NC
NC
Debounced
1
Yes No
No Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
J40 Function
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used