Lattice Semiconductor XP2 Advanced User Manual page 9

LatticeXP2 Advanced
Lattice Semiconductor Evaluation Board User's Guide
The 16-pin socket will allow connection to PLL clock pin A2 when the top of the oscillator is aligned to socket pins 1
and 16. Note that the SMA connector J12 is shared with the on-board oscillator. When installing the oscillator to
connect the clock to PLL clock pin A2, the SMA connector J12 cannot be used and the jumper on J17 needs to be
installed.
When the bottom of the oscillator is aligned to socket pins 8 and 9, the clock is provided to primary clock pin L4.
Figure 2. On-board Oscillator
SPI Serial Flash
SPI Serial Flash are available in three package styles. The device used this board is an 8-pin, 16-Mbit, sufficient to
store two bitstreams simultaneously in order to support SPIm mode.
Configuration/Programming Headers
Four programming headers are provided on the evaluation board, providing access to the LatticeXP2, MachXO™,
and ispPAC-POWR1220AT8 and LatticeXP2 SPI Slave JTAG ports. The JTAG connectors J25, J32, J39 and J40
are 1x10 headers. The JTAG ports for the LatticeXP2 and ispPAC-POWR1220AT8 devices can be configured as
loop-through connectors to allow for easy daisy chaining of multiple boards. With proper jumper selection (see the
next section) standard IDC ribbon cable can be used without the need to swap any wires on the cable.
The pinouts for these headers are provided in the following tables.
®
A USB ispDOWNLOAD cable is included with each LatticeXP2 Advanced Evaluation Board. When using the 1x8
cable adapter, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable or USB cable. Always connect an ispDOWNLOAD Cable's GND pin (black wire), before connecting
any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and ren-
der the board inoperable.
LatticeXP2 Configuration
Two programming headers, J39 and J40, are provided on the evaluation board, providing access to the LatticeXP2
JTAG port and the ispPAC-POWR1220AT8 JTAG port. The pinouts for the headers are provided in Table 11.
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