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CP6003-SA
Table 1-1:
CP6003-SA Main Specifications (Continued)
FEATURES
Intel® QM67
Graphics controller
CompactPCI
ID 1044-9757, Rev. 2.0
Mobile Intel® QM67 Express Chipset:
Two x4 or eight x1 PCI Express 2.0 ports operating at 5 GT/s (only one
•
x4 PCI Express port is used on the CP6003-SA)
SATA host controller with six ports and RAID 0/1/5/10 support
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Two SATA 6 Gb/s ports accessible via onboard connectors
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Four SATA 3 Gb/s ports accessible via rear I/O
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USB 2.0 host interface with up to 14 USB ports available (only six ports
•
are used on the CP6003-SA)
Integrated Ethernet controller
•
SPI flash interface support
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Low Pin Count (LPC) interface
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Power management logic support
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Enhanced DMA controller, interrupt controller, and timer functions
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System Management Bus (SMBus) compatible with most I²C™ devices
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DMI 2.0 with 5 GT/s and FDI interfaces to the processor
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High Definition Audio (HDA) interface
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Analog display port
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Three digital display ports
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Integrated RTC
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High-performance 3D graphics controller integrated in the processor:
Support for two independent displays
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Supports analog displays (CRT) up to a resolution of 2048 x 1536
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pixels with 32-bit color @ 75 Hz
Supports digital displays (HDMI/DVI) up to a resolution of 1920 x
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1200 pixels @ 60 Hz
Dynamic Video Memory Technology (DVMT)
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Compliant with CompactPCI Specification PICMG 2.0 R 3.0:
System controller operation
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64-bit / 66 MHz PCI or PCI-X master interface with dedicated PCIe-to-
•
PCI-X bridge
3.3V or 5V signaling levels (universal signaling support)
•
Compliant with the Packet Switching Specification PICMG 2.16.
The CP6003-SA supports System Master hot swap functionality and applica-
tion-dependent hot swap functionality when used in a peripheral slot.
When used as a System Master, the CP6003-SA supports individual clocks for
each slot and the ENUM signal handling is in compliance with the PICMG 2.1
Hot Swap Specification.
When installed in a peripheral slot, the CP6003-SA is isolated from the Com-
pactPCI bus. It receives power from the backplane and supports rear I/O and,
if the system supports it, packet switching (in this case up to two channels of
Gigabit Ethernet).
SPECIFICATIONS
Introduction
Page 1 - 11
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