Zero Balance; Simulation Of Digital Outputs - HBM MP85A Operating Manual

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Timing diagram for a transducer test
Output transducer test
result

8.4 Zero balance

The zero balance can be triggered via the digital input or via the bus signal. At
low filter limit frequencies, the filter settling time must be waited before the
zero balance. A pulse of minimum 5 ms duration at the digital input is neces-
sary for the zero balance. The zero balance is completed another 5 ms later.
Timing diagram for a zero balance
Inputs
Zero setting
Input
START

8.5 Simulation of digital outputs

It can be helpful, particularly during start up or service, to check the system
components and processes downstream of the digital outputs through simula-
tion and activation. The digital outputs of the MP85A process controller can be
activated/deactivated via software commands for this purpose.
The data word configuration to be transmitted for activating/deactivating the
digital outputs depends on the configuration of the data word bits on the digital
outputs.
HBM
Input
Transducer test
min. 5 ms
1
Settling time, e.g. for a 100 Hz filter: 20 ms
MP85A process controller
min. 5 ms
1
Typically 10 ms
0
0
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