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Board Description and Memory Maps
1
1-40
EN_LM1 When the EN_LM1 bit is set, an LM/SIG Interrupt 1 is
generated and the LM1 bit is asserted.
EN_LM0 When the EN_LM0 bit is set, an LM/SIG Interrupt 0 is
generated and the LM0 bit is asserted.
SIG1
SIG1 status bit. This bit can only be set by the SET_LM1
control bit. It can only be cleared by a reset or by writing
a 1 to the CLR_LM1 control bit.
SIG0
SIG0 status bit. This bit can only be set by the SET_LM0
control bit. It can only be cleared by a reset or by writing
a 1 to the CLR_LM0 control bit.
LM1
LM1 status bit. This bit can be set by either the location
monitor function or the SET_LM1 control bit. LM1
correspond to offset 3 from the location monitor base
address. This bit can only be cleared by a reset or by
writing a 1 to the CLR_LM1 control bit.
LM0
LM0 status bit. This bit can be set by either the location
monitor function or the SET_LM0 control bit. LM0
correspond to offset 1 from the location monitor base
address. This bit can only be cleared by a reset or by
writing a 1 to the CLR_LM0 control bit.
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