Processor 0 External Cache Control Register (P0Xccr); Processor 1 External Cache Control Register (P1Xccr); Cpu Control Register - Motorola MVME2300 Series Programmer's Reference Manual

Board Description and Memory Maps
1

Processor 0 External Cache Control Register (P0XCCR)

Processor 1 External Cache Control Register (P1XCCR)

CPU Control Register

REG
BIT
FIELD
OPER
RESET
1-30
The MVME2300 and MVME2300SC boards do not implement this
register. Writes to this register location ($FEF88100) will have no system
effects. Reads from this register location will return undefined data.
The MVME2300 and MVME2300SC boards do not implement this
register. Writes to this register location ($FEF88200) will have no system
effects. Reads from this register location will return undefined data.
The CPU Control register is accessed via the RD[32:39] data lines of the
upper Falcon device. This 8-bit register is defined as follows:
CPU Control Register - $FEF88300
0 1 2
R R R
1 0 0
LEMODE Little Endian Mode. This bit must be set in conjunction
with the LEND bit in the Raven for little-endian mode.
P0_TBEN Processor 0 Time Base Enable. When this bit is cleared,
the TBEN pin of the processor will be driven low.
3 4 5
R/W R R
1 X X
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6 7
R R
X X