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DRAM Attributes Register ....................................................................... 3-33
DRAM Base Register................................................................................ 3-35
CLK Frequency Register........................................................................... 3-35
ECC Control Register ............................................................................... 3-36
Error Logger Register ............................................................................... 3-39
Error Address Register .............................................................................. 3-42
Scrub/Refresh Register.............................................................................. 3-43
Refresh/Scrub Address Register ............................................................... 3-44
ROM A Base/Size Register....................................................................... 3-45
ROM B Base/Size Register ....................................................................... 3-48
DRAM Tester Control Registers............................................................... 3-50
32-Bit Counter........................................................................................... 3-50
Test SRAM................................................................................................ 3-50
Power-Up Reset Status Register 1 ............................................................ 3-51
Power-Up Reset Status Register 2 ............................................................ 3-51
External Register Set................................................................................. 3-52
Software Considerations.......................................................................................... 3-53
Parity Checking on the PowerPC Bus .............................................................. 3-53
Programming ROM/Flash Devices .................................................................. 3-53
Writing to the Control Registers....................................................................... 3-53
Sizing DRAM................................................................................................... 3-54
ECC Codes ....................................................................................................... 3-57
Data Paths......................................................................................................... 3-60
CHAPTER 4
Universe (VMEbus to PCI) Chip
Introduction ............................................................................................................... 4-1
Features...................................................................................................................... 4-1
Block Diagram........................................................................................................... 4-3
Functional Description .............................................................................................. 4-3
VMEbus Interface .............................................................................................. 4-4
Universe as VMEbus Slave......................................................................... 4-4
Universe as VMEbus Master ...................................................................... 4-5
PCI Bus Interface ............................................................................................... 4-5
Universe as PCI Slave ................................................................................. 4-6
Universe as PCI Master............................................................................... 4-6
Interrupter ........................................................................................................... 4-6
VMEbus Interrupt Handling ....................................................................... 4-7
DMA Controller ................................................................................................. 4-7
Universe Control and Status Registers (UCSR)................................................. 4-8
Universe Register Map................................................................................ 4-9
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