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REN
WEN
WPEN
IOM
General-Purpose Registers
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
These general-purpose read/write registers are provided for inter-process
message passing or general-purpose storage. They do not control any
hardware.
PCI Registers
The PCI Configuration registers are compliant with the configuration
register set described in the PCI Local Bus Specification, Revision 2.0.
The CONFIG_ADDRESS and CONFIG_DATA registers described in
this section are accessed within PCI I/O space.
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Read Enable. If set, the corresponding MPC slave is
enabled for read transactions.
Write Enable. If set, the corresponding MPC slave is
enabled for write transactions.
Write-Post Enable. If set, write-posting is enabled for the
corresponding MPC slave.
PCI I/O Mode. If set, the corresponding MPC slave will
generate PCI I/O cycles using spread addressing as
defined in the section on
Cycles. When clear, the corresponding MPC slave will
generate PCI I/O cycles using contiguous addressing.
GPREG0 (Upper) - $FEFF0070
GPREG0 (Lower) - $FEFF0074
GPREG1 (Upper) - $FEFF0078
GPREG1 (Lower) - $FEFF007C
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
GPREGx
R/W
$00000000
Raven Registers
Generating PCI Memory and I/O
1
1
2
2
2
2
2
2
2
8
9
0
1
2
3
4
5
6
2
2
2
2
3
3
7
8
9
0
1
2-47
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