Dram Base Register; Clk Frequency Register - Motorola MVME2300 Series Programmer's Reference Manual

DRAM Base Register

Address
Bit
Name
RAM A BASE
Operation
READ/WRITE
Reset
0 PL
RAM A/B/C/D BASE

CLK Frequency Register

Address
Bit
Name
CLK
FREQUENCY
Operation
READ/WRITE
Reset
42 P
CLK FREQUENCY
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$FEF80018
RAM B BASE RAM C BASE
READ/WRITE READ/WRITE
0 PL
These control bits define the base address for their block's
DRAM. RAM A/B/C/D BASE bits 0-7/8-15/16-23/24-
31 correspond to PowerPC 60x address bits 0 - 7. For
larger DRAM sizes, the lower significant bits of A/B/C/D
BASE are ignored. This means that the block's base
address will always appear at an even multiple of its size.
Note that bit 0 is MSB.
Also note that the combination of RAM_X_BASE and
ram_x_siz should never be programmed such that
DRAM responds at the same address as the CSR,
ROM/Flash, External Register Set, or any other slave on
the PowerPC bus.
$FEF80020
READ ZERO READ ZERO
X
These bits should be programmed with the hexadecimal
value of the operating CLOCK frequency in MHz (i.e.
$42 for 66MHz). When these bits are programmed this
way, the chip's prescale counter produces a 1MHz output.
Programming Model
RAM D BASE
READ/WRITE
0 PL 0 PL
X
3
3-35