Figure 2-5. Pci To Mpc Address Translation - Motorola MVME2300 Series Programmer's Reference Manual

Figure 2-5. PCI to MPC Address Translation

All Raven address decoders are prioritized so that programming multiple
decoders to respond to the same address is not a problem. When the PCI
address falls into the range of more than one decoder, only the highest
priority one will respond. The decoders are prioritized as shown below.
RavenMPIC Control Registers
The RavenMPIC control registers are located within either PCI memory or
PCI I/O space using traditional PCI-defined base registers within the
predefined 64-byte header. Refer to the section on
Controller
http://www.motorola.com/computer/literature
PCI Bus Address
PSOFFx Register
MPC Bus Address
Decoder
PCI Slave 0
PCI Slave 1
PCI Slave 2
PCI Slave 3
for more information.
Functional Description
8 0 8 0 1 2 3 4
31 16 15
+
9 0 0 0
31 16
=
1 0 8 0 1 2 3 4
0 15 16
Priority
highest
lowest
Raven Interrupt
0
31
2-13
2