Motorola MC9S12C-Family User Manual
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Motorola MC9S12C-Family User Manual

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in
different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's
technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
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©Motorola, Inc., 2002
MC9S12C Family
Device User Guide
V01.05
Covers also
MC9S12GC Family
Original Release Date: 25 JAN 2003
Revised: 11 FEBRUARY 2004
Motorola, Inc.
DOCUMENT NUMBER
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
9S12C128DGV1/D
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Summary of Contents for Motorola MC9S12C-Family

  • Page 1 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

  • Page 2: Revision History

    Revision History Version Revision Effective Number Date Date 00.01 25.JAN.03 25.JAN.03 00.02 07.FEB.03 07.FEB.03 00.03 25.FEB.03 25.FEB.03 00.04 15.APR.03 15.APR03 00.05 05.MAY.03 05.MAY.03 00.06 21.MAY.03 21.MAY.03 01.00 15.JUL.03 15.JUL03 01.01 12.AUG.03 12.AUG.03 01.02 20.NOV.03 20.NOV.03 01.03 27.NOV.03 27.NOV.03 01.04 27.JAN.04 27.JAN.04 01.05 11.FEB.04 11.FEB.04 Device User Guide —...

  • Page 3: Table Of Contents

    Table of Contents Section 1 Introduction Overview............23 Features .
  • Page 4 Device User Guide — 9S12C128DGV1/D V01.05 2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] ......62 2.3.21 PM5 / SCK —...
  • Page 5 Overview............68 Vectors .
  • Page 6 Device User Guide — 9S12C128DGV1/D V01.05 Section 16 RAM Block Description Section 17 Pulse Width Modulator (PWM) Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module (PIM) Block Description Appendix A Electrical Characteristics General............83 A.1.1 Parameter Classification .
  • Page 7 Reset, Oscillator and PLL..........109 B.6.1 Startup .
  • Page 8 Device User Guide — 9S12C128DGV1/D V01.05...
  • Page 9 Figure 1-1 MC9S12C-Family Block Diagram ....... . . 27 Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map .
  • Page 10 Device User Guide — 9S12C128DGV1/D V01.05 Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) ..130 Figure 19-1 Pin Assignments in 112-pin LQFP....... . 131 Figure 19-2 112-pin LQFP mechanical dimensions (case no.
  • Page 11 List of MC9S12C and MC9S12GC Family members....15 Table 0-3 MC9S12C-Family Part Number Coding......16 Table 0-4 MC9S12GC-Family Part Number Coding .
  • Page 12 Signal Properties ..........55 Table 2-2 MC9S12C-Family Power and Ground Connection Summary ... . . 64 Table 4-1 Mode Selection .
  • Page 13 Table C-2 SPI Master Mode Timing Characteristics......120 Table C-3 SPI Slave Mode Timing Characteristics......122 Table C-4 Expanded Bus Timing Characteristics (5V Range).
  • Page 14 Device User Guide — 9S12C128DGV1/D V01.05...

  • Page 15: Table 0-2 Mc9S12C-Family Package Option Summary

    Preface The Device User Guide provides information about the MC9S12C-Family as well the MC9S12GC-Family devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules.

  • Page 16: Figure 0-1 Order Part Number Coding

    The GC-Family members do not have the CAN module 4. I/O is the sum of ports capable to act as digital input or output. MC9S12 C32 (P)C FU Figure 0-1 Order Part number Coding Table 0-3 MC9S12C-Family Part Number Coding Mask Part Number MC9S12C128CFA16 Mask Temp.
  • Page 17 Mask Part Number Temp. MC9S12C128CPB16 -40˚C, 85˚C MC9S12C128CFU16 -40˚C, 85˚C MC9S12C128VFA16 -40˚C,105˚C MC9S12C128VPB16 -40˚C,105˚C MC9S12C128VFU16 -40˚C, 105˚C MC9S12C128MFA16 -40˚C,125˚C MC9S12C128MPB16 -40˚C,125˚C MC9S12C128MFU16 -40˚C, 125˚C MC9S12C128CFA25 -40˚C, 85˚C MC9S12C128CPB25 -40˚C, 85˚C MC9S12C128CFU25 -40˚C, 85˚C MC9S12C128VFA25 -40˚C,105˚C MC9S12C128VPB25 -40˚C,105˚C MC9S12C128VFU25 -40˚C, 105˚C MC9S12C128MFA25 -40˚C,125˚C MC9S12C128MPB25...
  • Page 18 Device User Guide — 9S12C128DGV1/D V01.05 Mask Part Number MC9S12C96VFA25 MC9S12C96VPB25 MC9S12C96VFU25 MC9S12C96PMFA25 0L09S MC9S12C96PMPB25 0L09S MC9S12C96PMFU25 0L09S MC9S12C96MFA25 MC9S12C96MPB25 MC9S12C96MFU25 MC9S12C64PCFA16 0L09S MC9S12C64PCPB16 0L09S MC9S12C64PCFU16 0L09S MC9S12C64CFA16 MC9S12C64CPB16 MC9S12C64CFU16 MC9S12C64PVFA16 0L09S MC9S12C64PVPB16 0L09S MC9S12C64PVFU16 0L09S MC9S12C64VFA16 MC9S12C64VPB16 MC9S12C64VFU16 MC9S12C64PMFA16 0L09S MC9S12C64PMPB16 0L09S...

  • Page 19: Table 0-4 Mc9S12Gc-Family Part Number Coding

    Mask Part Number MC9S12C64MFU25 MC9S12C32CFA16 1L45J MC9S12C32CPB16 1L45J MC9S12C32CFU16 1L45J MC9S12C32VFA16 1L45J MC9S12C32VPB16 1L45J MC9S12C32VFU16 1L45J MC9S12C32MFA16 1L45J MC9S12C32MPB16 1L45J MC9S12C32MFU16 1L45J MC9S12C32CFA25 1L45J MC9S12C32CPB25 1L45J MC9S12C32CFU25 1L45J MC9S12C32VFA25 1L45J MC9S12C32VPB25 1L45J MC9S12C32VFU25 1L45J MC9S12C32MFA25 1L45J MC9S12C32MPB25 1L45J MC9S12C32MFU25 1L45J Table 0-4 MC9S12GC-Family Part Number Coding Mask Part Number...
  • Page 20 Device User Guide — 9S12C128DGV1/D V01.05 Mask Part Number MC9S12GC64CFA25 MC9S12GC64CPB25 MC9S12GC64CFU25 MC9S12GC64PVFA25 0L09S MC9S12GC64PVPB25 0L09S MC9S12GC64PVFU25 0L09S MC9S12GC64VFA25 MC9S12GC64VPB25 MC9S12GC64VFU25 MC9S12GC64PMFA25 0L09S MC9S12GC64PMPB25 0L09S MC9S12GC64PMFU25 0L09S MC9S12GC64MFA25 MC9S12GC64MPB25 MC9S12GC64MFU25 MC9S12GC32PCFA25 1L45J MC9S12GC32PCPB25 1L45J MC9S12GC32PCFU25 1L45J MC9S12GC32CFA25 MC9S12GC32CPB25 MC9S12GC32CFU25 MC9S12GC32PVFA25 1L45J MC9S12GC32PVPB25 1L45J...

  • Page 21: Table 0-5 Document References

    Clock and Reset Generator (CRG) Block Guide Serial Communications Interface (SCI) Block Guide Serial Peripheral Interface (SPI) Block Guide Motorola Scalable CAN (MSCAN) Block Guide Pulse Width Modulator: 8 bit, 6 channel (PWM_8B6C) Block Guide Timer: 16 bit, 8 channel (TIM_16B8C) Block Guide...
  • Page 22 Device User Guide — 9S12C128DGV1/D V01.05...

  • Page 23: Section 1 Introduction

    In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. The MC9S12C-Family and the MC9S12GC-Family devices are available in 48, 52 and 80 pin QFP packages, with the 80 Pin version pin compatible to the HCS12 A, B and D- Family derivatives.
  • Page 24 – One 8-channel module with 10-bit resolution. – External conversion trigger capability • Available on MC9S12C-Family: One 1M bit per second, CAN 2.0 A, B software compatible module – Five receive and three transmit buffers – Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit –...

  • Page 25: Modes Of Operation

    – Pierce or low current Colpitts oscillator – Phase-locked loop clock frequency multiplier – Limp home mode in absence of external clock – Low power 0.5 to 16 MHz crystal oscillator reference clock • Operating frequency – 32MHz equivalent to 16MHz Bus Speed for single chip –...
  • Page 26 Device User Guide — 9S12C128DGV1/D V01.05 – Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Motorola use only) – Special Peripheral Mode (Motorola use only) • Low power modes – Stop Mode – Pseudo Stop Mode...

  • Page 27: Block Diagram

    1.4 Block Diagram Figure 1-1 MC9S12C-Family Block Diagram VSSR VDDR VDDX Voltage Regulator VSSX 16K, 32K, 64K, 96K, 128K Byte Flash VDD2 VSS2 VDD1 1K, 2K, 4K Byte RAM VSS1 Background MODC BKGD Debug12 Module VDDPLL Clock and VSSPLL Reset...

  • Page 28: Device Memory Map

    Device User Guide — 9S12C128DGV1/D V01.05 1.5 Device Memory Map Table 1-1 shows the device register map of the MC9S12C-Family after reset. The following figures (Figure 1-2, Figure 1-2, Figure 1-3 and Figure 1-4) illustrate the full device memory map with flash and RAM.

  • Page 29: Figure 1-2 Mc9S12C128 And Mc9S12Gc128 User Configurable Memory Map

    $0000 $0400 $3000 $4000 $8000 $C000 $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map Device User Guide —...

  • Page 30: Figure 1-3 Mc9S12C96 User Configurable Memory Map

    Device User Guide — 9S12C128DGV1/D V01.05 $0000 $0400 $3000 $4000 $8000 $C000 $FF00 VECTORS $FFFF NORMAL SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 1-3 MC9S12C96 User Configurable Memory Map...

  • Page 31: Figure 1-4 Mc9S12C64 And Mc9S12Gc64 User Configurable Memory Map

    $0000 $0400 $3000 $4000 $8000 $C000 $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map Device User Guide —...

  • Page 32: Figure 1-5 Mc9S12C32 And Mc9S12Gc32 User Configurable Memory Map

    Device User Guide — 9S12C128DGV1/D V01.05 $0000 $0400 $3800 $4000 $8000 $C000 $FF00 VECTORS $FFFF NORMAL SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map...

  • Page 33: Detailed Register Map

    $0000 $0400 $3800 $4000 $8000 $C000 $FF00 VECTORS $FFFF NORMAL SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes Figure 1-6 MC9S12GC16 User Configurable Memory Map 1.6 Detailed Register Map...
  • Page 34 Device User Guide — 9S12C128DGV1/D V01.05 $0000 - $000F Address Name Read: $0000 PORTA Write: Read: $0001 PORTB Write: Read: $0002 DDRA Write: Read: $0003 DDRB Write: Read: $0004 Reserved Write: Read: $0005 Reserved Write: Read: $0006 Reserved Write: Read: $0007 Reserved Write:...
  • Page 35 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) Address Name Bit 7 Read: $0012 INITEE EE15 Write: Read: $0013 MISC Write: Read: $0014 Reserved Write: $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) Address Name Bit 7 Read:...
  • Page 36 Device User Guide — 9S12C128DGV1/D V01.05 $001C - $001D Address Name Read: reg_sw0 $001C MEMSIZ0 Write: Read: rom_sw1 rom_sw0 $001D MEMSIZ1 Write: $001E - $001E Address Name Read: $001E INTCR Write: $001F - $001F Address Name Read: $001F HPRIO Write: $0020 - $002F Address Name...
  • Page 37 $0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug) Address Name Bit 7 DBGCAL read $002C Bit 7 BKP0L write DBGCBX read $002D BKP1X write DBGCBH read $002E Bit 15 BKP1H write DBGCBL read $002F Bit 7 BKP1L write $0030 - $0031...
  • Page 38 Device User Guide — 9S12C128DGV1/D V01.05 $0034 - $003F Address Name Read: $003B RTICTL Write: Read: $003C COPCTL Write: Read: FORBYP $003D TEST ONLY Write: Read: CTCTL $003E TEST ONLY Write: Read: $003F ARMCOP Write: $0040 - $006F Address Name Read: $0040 TIOS...
  • Page 39 Address Name Bit 7 Read: $0050 TC0 (hi) Bit 15 Write: Read: $0051 TC0 (lo) Bit 7 Write: Read: $0052 TC1 (hi) Bit 15 Write: Read: $0053 TC1 (lo) Bit 7 Write: Read: $0054 TC2 (hi) Bit 15 Write: Read: $0055 TC2 (lo) Bit 7...
  • Page 40 Device User Guide — 9S12C128DGV1/D V01.05 Address Name Read: $0068 Reserved Write: Read: $0069 Reserved Write: Read: $006A Reserved Write: Read: $006B Reserved Write: Read: $006C Reserved Write: Read: $006D Reserved Write: Read: $006E Reserved Write: Read: $006F Reserved Write: $0070 - $007F Read: $0070...
  • Page 41 $0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Read: CCF7 $008B ATDSTAT1 Write: Read: $008C Reserved Write: Read: $008D ATDDIEN Bit 7 Write: Read: $008E Reserved Write: Read: Bit7 $008F PORTAD0 Write: Read: Bit15 $0090...
  • Page 42 Device User Guide — 9S12C128DGV1/D V01.05 $00C8 - $00CF Address Name Read: $00C8 SCIBDH Write: Read: $00C9 SCIBDL Write: Read: $00CA SCICR1 Write: Read: $00CB SCICR2 Write: Read: $00CC SCISR1 Write: Read: $00CD SCISR2 Write: Read: $00CE SCIDRH Write: Read: $00CF SCIDRL Write:...
  • Page 43 $00E0 - $00FF PWM (Pulse Width Modulator) Address Name Bit 7 Read: $00E0 PWME Write: Read: $00E1 PWMPOL Write: Read: $00E2 PWMCLK Write: Read: $00E3 PWMPRCLK Write: Read: $00E4 PWMCAE Write: Read: $00E5 PWMCTL Write: Read: PWMTST $00E6 Test Only Write: Read: $00E7...
  • Page 44 Device User Guide — 9S12C128DGV1/D V01.05 Address Name Read: $00F7 PWMPER5 Write: Read: $00F8 PWMDTY0 Write: Read: $00F9 PWMDTY1 Write: Read: $00FA PWMDTY2 Write: Read: $00FB PWMDTY3 Write: Read: $00FC PWMDTY4 Write: Read: $00FD PWMDTY5 Write: Read: $00FE Reserved Write: Read: $00FF Reserved...
  • Page 45 Reserved Write: Read: $010F Reserved Write: $0110 - $013F Reserved Read: $0110 Reserved - $003F Write: $0140 - $017F CAN (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Read: $0140 CANCTL0 RXFRM Write: Read: $0141 CANCTL1 CANE Write: Read:...

  • Page 46: Table 1-2 Detailed Mscan Foreground Receive And Transmit Buffer Layout

    Write: Read: $xxxF CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: $xx10 Standard ID Read: Write: CAN (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 RXERR7 RXERR6 RXERR5 RXERR4 TXERR7 TXERR6 TXERR5 TXERR4 FOREGROUND RECEIVE BUFFER see Table 1-2...
  • Page 47 Address Name Bit 7 Extended ID Read: ID20 CANxTIDR1 Write: $xx11 Standard ID Read: Write: Extended ID Read: ID14 CANxTIDR2 Write: $xx12 Standard ID Read: Write: Extended ID Read: CANxTIDR3 Write: $xx13 Standard ID Read: Write: Read: $xx14- CANxTDSR0 - $xx1B CANxTDSR7 Write:...
  • Page 48 Device User Guide — 9S12C128DGV1/D V01.05 Read: $0249 PTIS Write: Read: $024A DDRS Write: Read: $024B RDRS Write: Read: $024C PERS Write: Read: $024D PPSS Write: Read: $024E WOMS Write: Read: $024F Reserved Write: Read: $0250 Write: Read: $0251 PTIM Write: Read: $0252...
  • Page 49 Read: $0261 Reserved Write: Read: $0262 Reserved Write: Read: $0263 Reserved Write: Read: $0264 Reserved Write: Read: $0265 Reserved Write: Read: $0266 Reserved Write: Read: $0267 Reserved Write: Read: $0268 PTJ7 Write: Read: PTIJ7 $0269 PTIJ Write: Read: $026A DDRJ DDRJ7 Write: Read:...

  • Page 50: Part Id Assignments

    Device User Guide — 9S12C128DGV1/D V01.05 $0280 - $03FF Address Name Read: $0280 Reserved - $2FF Write: Read: $0300 - Unimplemented $03FF Write: 1.7 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset).
  • Page 51 Table 1-4 Memory size registers Device MC9S12C32, MC9S12GC32 MC9S12C64, MC9S12GC64 MC9S12C96 MC9S12C128, MC9S12GC128 Device User Guide — 9S12C128DGV1/D V01.05 Register name Value MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1...

  • Page 52: Section 2 Signal Description

    Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family MC9S12C-Family...

  • Page 53: Figure 2-2 Pin Assignments In 52 Lqfp For Mc9S12C-Family

    VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD * Signals shown in Bold italic are not available on the 48 Pin Package Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family Device User Guide — 9S12C128DGV1/D V01.05 MC9S12C-Family MC9S12GC-Family VDDA PAD07/AN07 PAD06/AN06...

  • Page 54: Figure 2-3 Pin Assignments In 48 Lqfp For Mc9S12C-Family

    Device User Guide — 9S12C128DGV1/D V01.05 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family MC9S12C-Family MC9S12GC-Family VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 XIRQ/PE0...

  • Page 55: Signal Properties Summary

    2.2 Signal Properties Summary Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 EXTAL — — XTAL — — RESET — — — — TEST — BKGD MODC TAGHI NOACC XCLKS IPIPE1 MODB IPIPE0 MODA ECLK — LSTRB TAGLO —...

  • Page 56: Pin Initialization For 48 & 52 Pin Lqfp Bond-Out Versions

    Device User Guide — 9S12C128DGV1/D V01.05 Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 PP[2:0] KWP[2:0] PW[2:0] PJ[7:6] KWJ[7:6] — — MOSI — — MISO — TXCAN — RXCAN — PS[3:2] — — — — PT[7:5] IOC[7:5] —...

  • Page 57: Detailed Signal Descriptions

    Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.

  • Page 58: Bkgd / Taghi / Modc - Background Debug, Tag High & Mode Pin

    Device User Guide — 9S12C128DGV1/D V01.05 2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue.

  • Page 59: Figure 2-5 Colpitts Oscillator Connections (Pe7=1)

    Device User Guide — 9S12C128DGV1/D V01.05 EXTAL Crystal or ceramic resonator XTAL VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal .Please contact the crystal manufacturer for crystal DC Figure 2-5 Colpitts Oscillator Connections (PE7=1) EXTAL Crystal or...

  • Page 60: Pe6 / Modb / Ipipe1 - Port E I/O Pin 6

    Device User Guide — 9S12C128DGV1/D V01.05 2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1}.

  • Page 61: Pe1 / Irq - Port E Input Pin [1] / Maskable Interrupt Pin

    Device User Guide — 9S12C128DGV1/D V01.05 2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always enabled and configured to level-sensitive triggering out of reset.

  • Page 62: Pp[5:0] / Kwp[5:0] / Pw[5:0] - Port P I/O Pins [5:0]

    Device User Guide — 9S12C128DGV1/D V01.05 2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0] PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. PP[5:0] are also shared with the PWM output signals, PW[5:0].

  • Page 63: Ps[3:2] - Port S I/O Pins [3:2]

    Device User Guide — 9S12C128DGV1/D V01.05 2.3.27 PS[3:2] — Port S I/O Pins [3:2] PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48 / 52 pin package versions. 2.3.28 PS1 / TXD — Port S I/O Pin 1 PS1 is a general purpose input or output pin and the transmit pin, TXD, of Serial Communication Interface (SCI).

  • Page 64: Vdda, Vssa - Power Supply Pins For Atd And Vreg

    Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. Table 2-2 MC9S12C-Family Power and Ground Connection Summary Nominal Mnemonic...

  • Page 65: Section 4 Modes Of Operation

    The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. EXTAL XTAL Section 4 Modes of Operation...

  • Page 66: Security

    Device User Guide — 9S12C128DGV1/D V01.05 latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map.

  • Page 67: Securing The Microcontroller

    Device User Guide — 9S12C128DGV1/D V01.05 of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters. 4.3.1 Securing the Microcontroller Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module.

  • Page 68: Stop

    Device User Guide — 9S12C128DGV1/D V01.05 4.4.1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts. 4.4.2 Pseudo Stop This mode is entered by executing the CPU STOP instruction.

  • Page 69: Resets

    $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 Real Time Interrupt $FFEE, $FFEF Standard Timer channel 0 $FFEC, $FFED Standard Timer channel 1 $FFEA, $FFEB Standard Timer channel 2 $FFE8, $FFE9 Standard Timer channel 3 $FFE6, $FFE7 Standard Timer channel 4 $FFE4, $FFE5 Standard Timer channel 5 $FFE2, $FFE3...

  • Page 70: Reset Summary Table

    Device User Guide — 9S12C128DGV1/D V01.05 changed to known start-up states. Refer to the respective module Block User Guides for register reset states. 5.3.1 Reset Summary Table Reset Power-on Reset External Reset Low Voltage Reset Clock Monitor Reset COP Watchdog Reset 5.3.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states.

  • Page 71: Bdm Alternate Clock

    The BDM section of S12 Core User Guide reference to alternate clock is equivalent to oscillator clock. 6.1.3 Extended Address Range Emulation Implications In order to emulate the MC9S12GC or MC9S12C-Family devices, external addressing of a 128K memory map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK[2:0].

  • Page 72: Section 7 Voltage Regulator (Vreg) Block Description

    Device User Guide — 9S12C128DGV1/D V01.05 To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE should not be changed by software. Section 7 Voltage Regulator (VREG) Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator. 7.1 Device-specific information The VREG is part of the IPBus domain.
  • Page 73 Table 8-1 Recommended External Component Values Component Purpose VDD1 filter capapcitor VDD2 filter capacitor (80 QFP only) VDDA filter capacitor VDDR filter capacitor VDDPLL filter capacitor VDDX filter capacitor OSC load capacitor OSC load capacitor PLL loop filter capacitor PLL loop filter capacitor DC cutoff capacitor PLL loop filter resistor R2 / R...

  • Page 74: Figure 8-1 Recommended Pcb Layout (48 Lqfp)

    Device User Guide — 9S12C128DGV1/D V01.05 VDD1 VSS1 VSSR VDDR Note: Oscillator in Colpitts mode. Figure 8-1 Recommended PCB Layout (48 LQFP) VSSA VSSX VDDA VSSPLL VDDPLL...

  • Page 75: Figure 8-2 Recommended Pcb Layout (52 Lqfp)

    Device User Guide — 9S12C128DGV1/D V01.05 NOTE: Oscillator in Colpitts mode. VSSA VSSX VDDA VDD1 VSS1 VSSR VDDR VSSPLL VDDPLL Figure 8-2 Recommended PCB Layout (52 LQFP)

  • Page 76: Figure 8-3 Recommended Pcb Layout (80 Qfp)

    Device User Guide — 9S12C128DGV1/D V01.05 NOTE: Oscillator in Colpitts mode. VSSA VSSX VDDA VDD1 VSS2 VSS1 VDD2 VSSR VDDR VSSPLL VDDPLL Figure 8-3 Recommended PCB Layout (80 QFP)

  • Page 77: Figure 8-4 Recommended Pcb Layout For 48 Lqfp Pierce Oscillator

    Device User Guide — 9S12C128DGV1/D V01.05 VSSA VSSX VDDA VDD1 VSS1 VSSR VDDR VSSPLL VDDPLL Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator...

  • Page 78: Figure 8-5 Recommended Pcb Layout For 52 Lqfp Pierce Oscillator

    Device User Guide — 9S12C128DGV1/D V01.05 VSSA VSSX VDDA VDD1 VSS1 VSSR VDDR VSSPLL VDDPLL Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator...

  • Page 79: Section 9 Clock Reset Generator (Crg) Block Description

    VDD1 VSS1 Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator Section 9 Clock Reset Generator (CRG) Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module. 9.1 Device-specific information The CRG is part of the IPBus domain. Device User Guide —...

  • Page 80: Xclks

    Device User Guide — 9S12C128DGV1/D V01.05 The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset.

  • Page 81: Section 16 Ram Block Description

    Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator Module. Section 18 MSCAN Block Description Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module. This module is not available on the MC9GC-Family Members.
  • Page 82 Device User Guide — 9S12C128DGV1/D V01.05 Consult the PIM_9C32 Block User Guide for information about the Port Integration Module for all versions of the MC9DS12GC and MC9S12C-Family. The MODRR register within the PIM allows for mapping of PWM channels to PortT in the absence of PortP pins for the low pin count packages.

  • Page 83: Appendix A Electrical Characteristics

    A.1 General NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. NOTE: The parts are specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range...

  • Page 84: Pins

    Device User Guide — 9S12C128DGV1/D V01.05 VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX;...

  • Page 85: Absolute Maximum Ratings

    A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit.

  • Page 86: Esd Protection And Latch-Up Immunity

    Device User Guide — 9S12C128DGV1/D V01.05 A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model.

  • Page 87: Power Dissipation And Thermal Characteristics

    NOTE: Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Rating I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage PLL Supply Voltage Voltage Difference VDDX to VDDA Voltage Difference VSSX to VSSR and VSSA...
  • Page 88 Device User Guide — 9S12C128DGV1/D V01.05 Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT I DD V DD Which is the sum of all output currents on I/O ports associated with VDDX and VDDM. For R is valid: DSON...

  • Page 89: I/O Characteristics

    Which is the sum of all output currents on I/O ports associated with VDDX and VDDR. Table A-5 Thermal Package Characteristics Thermal Resistance LQFP48, single layer PCB Thermal Resistance LQFP48, double sided PCB with 2 internal planes Junction to Board LQFP48 Junction to Case LQFP48 Junction to Package Top LQFP48 Thermal Resistance LQFP52, single sided PCB...
  • Page 90 Device User Guide — 9S12C128DGV1/D V01.05 Conditions are 4.5< VDDX <5.5V Termperature from -40˚C to +140˚C, unless otherwise noted Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis Input Leakage Current (pins in high ohmic input mode) or V Output High Voltage (pins in output mode)
  • Page 91 Conditions are VDDX=3.3V +/-10%, Termperature from -40˚C to +140˚C, unless otherwise noted Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis Input Leakage Current (pins in high ohmic input mode) or V Output High Voltage (pins in output mode) Partial Drive I OH = –0.75mA Output High Voltage (pins in output mode) Full Drive I OH = –4mA...

  • Page 92: Supply Currents

    Device User Guide — 9S12C128DGV1/D V01.05 A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.
  • Page 93 Table A-8 Supply Current Characteristics for MC9S12C32 Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted Run Supply Current Single Chip Wait Supply current Pseudo Stop Current (RTI and COP disabled) Pseudo Stop Current (RTI and COP enabled) Stop Current NOTES: 1.
  • Page 94 Device User Guide — 9S12C128DGV1/D V01.05 Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128 Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted Run Supply Current Single Chip, Wait Supply current Pseudo Stop Current (RTI and COP disabled) Pseudo Stop Current (RTI and COP enabled) Stop Current NOTES:...

  • Page 95: Appendix B Electrical Specifications

    NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Motorola and are subject to change without notice. Device User Guide — 9S12C128DGV1/D V01.05 Symbol 2.97...

  • Page 96: Chip Power-Up And Lvi/Lvr Graphical Explanation

    Device User Guide — 9S12C128DGV1/D V01.05 B.2 Chip Power-up and LVI/LVR graphical explanation Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1. Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) LVID LVIA...

  • Page 97: Capacitive Loads

    B.3.2 Capacitive Loads The capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielectricum are required. Table B-2 Voltage Regulator - Capacitive Loads Characteristic VDD external capacitive load VDDPLL external capacitive load Device User Guide — 9S12C128DGV1/D V01.05 Symbol Typical DDext...
  • Page 98 Device User Guide — 9S12C128DGV1/D V01.05...

  • Page 99: Atd Characteristics

    B.4 ATD Characteristics This section describes the characteristics of the analog to digital converter. VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is bonded to the VSSA pin. The ATD is specified and tested for both the 3.3V and 5V range.

  • Page 100: Factors Influencing Accuracy

    Device User Guide — 9S12C128DGV1/D V01.05 beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped Table B-4 ATD Operating Characteristics Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V Num C Rating Reference Potential...
  • Page 101 B.4.3.3 Current injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions.

  • Page 102: Atd Accuracy (5V Range)

    Device User Guide — 9S12C128DGV1/D V01.05 B.4.4 ATD accuracy (5V Range) Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table B-6 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted = 5.12V.
  • Page 103 For the following definitions see also Figure B-2. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. The Integral Non-Linearity (INL) is defined as the sum of all DNLs: INL n Device User Guide — 9S12C128DGV1/D V01.05 –...

  • Page 104: Figure B-2 Atd Accuracy Definitions

    Device User Guide — 9S12C128DGV1/D V01.05 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 3.25 9.75 13 16.25 19.5 22.75 26 Figure B-2 ATD Accuracy Definitions NOTE: Figure B-2 shows only definitions, for specification values refer to Table B-6 . 10-Bit Absolute Error Boundary 8-Bit Absolute Error Boundary Ideal Transfer Curve...

  • Page 105: Nvm, Flash And Eeprom

    B.5 NVM, Flash and EEPROM B.5.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency f is required for performing program or erase operations. The NVM modules NVMOSC do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum.
  • Page 106 Device User Guide — 9S12C128DGV1/D V01.05 B.5.1.3 Sector Erase Erasing either a 512 byte or 1024 byte Flash sector takes: The setup times can be ignored for this operation. B.5.1.4 Mass Erase Erasing a NVM block takes: This is independent of sector size. The setup times can be ignored for this operation.

  • Page 107: Nvm Reliability

    B.5.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at 2ppm defects over lifetime at the operating conditions noted.
  • Page 108 Device User Guide — 9S12C128DGV1/D V01.05...

  • Page 109: Reset, Oscillator And Pll

    B.6 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). B.6.1 Startup Table B-10 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide. Conditions are shown in Table A-4 unless otherwise noted POR release level POR assert level...

  • Page 110: Oscillator

    Device User Guide — 9S12C128DGV1/D V01.05 B.6.1.4 External Reset When external reset is asserted for a time greater than PW the CRG module generates an internal RSTL reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.

  • Page 111: Phase Locked Loop

    time t . The device features a clock monitor. A time-out is asserted if the frequency of the incoming UPOSC clock signal is below the Clock Monitor FailureAssert Frequency f Table B-11 Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Crystal oscillator range (Colpitts) Crystal oscillator range (Pierce) Startup Current...

  • Page 112: Figure B-3 Basic Pll Functional Diagram

    Device User Guide — 9S12C128DGV1/D V01.05 refdv+1 Figure B-3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K and i from Table B-12. The grey boxes show the calculation for f for f = 4MHz and a 25MHz bus clock.
  • Page 113 And finally the frequency relationship is defined as With the above values the resistance can be calculated. The example is shown for a loop bandwidth =10kHz: ---------------------------- - The capacitance C can now be calculated as: --------------------- - The capacitance C should be chosen in the range of: B.6.3.2 Jitter Information The basic functionality of the PLL is shown in Figure B-3.

  • Page 114: Figure B-4 Jitter Definitions

    Device User Guide — 9S12C128DGV1/D V01.05 min1 max1 The relative deviation of t is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: For N < 100, the following equation is a good fit for the maximum jitter: J(N) Figure B-5 Maximum bus clock jitter approximation minN...
  • Page 115 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Conditions are shown in Table A-4 unless otherwise noted Num C Rating P Self Clock Mode frequency D VCO locking range Lock Detector transition from Acquisition to Tracking mode...
  • Page 116 Device User Guide — 9S12C128DGV1/D V01.05...

  • Page 117: Mscan

    B.7 MSCAN Table B-13 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass Device User Guide — 9S12C128DGV1/D V01.05 Rating Symbol...
  • Page 118 Device User Guide — 9S12C128DGV1/D V01.05...

  • Page 119: Spi

    B.8 SPI Appendix C Electrical Specifications This section provides electrical parametrics and ratings for the SPI. In Table C-1 the measurement conditions are listed. Description Drive mode Load capacitance C LOAD, on all outputs Thresholds for delay measurement points C.1 Master Mode In Figure C-1 the timing diagram for master mode with transmission format CPHA=0 is depicted.

  • Page 120: Figure C-2 Spi Master Timing (Cpha=1)

    Device User Guide — 9S12C128DGV1/D V01.05 (OUTPUT) (CPOL 0) (OUTPUT) (CPOL 1) (OUTPUT) MISO MSB IN (INPUT) MOSI PORT DATA MASTER MSB OUT (OUTPUT) 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure C-2 SPI Master Timing (CPHA=1) In Table C-2 the timing characteristics for master mode are listed.

  • Page 121: Slave Mode

    C.2 Slave Mode In Figure C-3 the timing diagram for slave mode with transmission format CPHA=0 is depicted. (INPUT) (CPOL 0) (INPUT) (CPOL 1) (INPUT) MISO SLAVE MSB (OUTPUT) note MOSI MSB IN (INPUT) NOTE: Not defined! Figure C-3 SPI Slave Timing (CPHA=0) In Figure C-4 the timing diagram for slave mode with transmission format CPHA=1 is depicted.

  • Page 122: Figure C-4 Spi Slave Timing (Cpha=1)

    Device User Guide — 9S12C128DGV1/D V01.05 (INPUT) (CPOL 0) (INPUT) (CPOL 1) (INPUT) MISO SLAVE note (OUTPUT) MOSI MSB IN (INPUT) NOTE: Not defined! Figure C-4 SPI Slave Timing (CPHA=1) In Table C-3 the timing characteristics for slave mode are listed. Table C-3 SPI Slave Mode Timing Characteristics Characteristic SCK Frequency...

  • Page 123: External Bus Timing

    C.3 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure C-5 with the actual timing values shown on table Table C-4. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. C.3.1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions.
  • Page 124 Device User Guide — 9S12C128DGV1/D V01.05 Table C-4 Expanded Bus Timing Characteristics (5V Range) Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40˚C to +140˚C, C Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high Address delay time Address valid time to E rise (PW Muxed address hold time...
  • Page 125 Table C-5 Expanded Bus Timing Characteristics (3.3V Range) Conditions are VDDX=3.3V+/-10%, Junction Temperature -40˚C to +140˚C, C Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high Address delay time Address valid time to E rise (PW Muxed address hold time Address hold to data valid Data hold to address...
  • Page 126 Device User Guide — 9S12C128DGV1/D V01.05...

  • Page 127: Appendix D Package Information

    Device User Guide — 9S12C128DGV1/D V01.05 Appendix D Package Information D.1 General This section provides the physical dimensions of the MC9S12C Family and MC9S12GC Family packages 48LQFP, 52LQFP, 80QFP.

  • Page 128: 80-Pin Qfp Package

    Device User Guide — 9S12C128DGV1/D V01.05 D.2 80-pin QFP package 0.20 0.05 A-B 0.20 SEATING PLANE DATUM PLANE DETAIL C Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B) DETAIL A DETAIL C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.

  • Page 129: 52-Pin Lqfp Package

    D.3 52-pin LQFP package 0.20 (0.008) H L-M SEATING PLANE 0.05 (0.002) VIEW AA Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03) Device User Guide — 9S12C128DGV1/D V01.05 4X 13 TIPS 0.20 (0.008) T L-M VIEW Y 0.10 (0.004) T VIEW AA 2X R 0.25 (0.010)

  • Page 130: 48-Pin Lqfp Package

    Device User Guide — 9S12C128DGV1/D V01.05 D.4 48-pin LQFP package 0.200 AB T-U 0.200 AC T-U BASE METAL 0.080 SECTION AE-AE Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) DETAIL Y DETAIL Y 0.080 AC TOP & BOTTOM DETAIL AD NOTES: DIMENSIONING AND TOLERANCING PER...

  • Page 131: Appendix E Emulation Information

    Appendix E Emulation Information E.1 General In order to emulate the MC9S12C and 9S12GC-Family devices, external addressing of a 128K memory map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK. This package version is for emulation only and not provided as a general production package.

  • Page 132: Pk[2:0] / Xaddr[16:14]

    Device User Guide — 9S12C128DGV1/D V01.05 E.1.1 PK[2:0] / XADDR[16:14] PK2-PK0 provide the expanded address XADDR[16:14] for the external bus. Refer to the S12 Core user guide for detailed information about external address page access. Internal Pull Resistor Pin Name Pin Name Power Description...

  • Page 133: 112-Pin Lqfp Package

    E.2 112-pin LQFP package 0.20 PIN 1 IDENT VIEW Y 0.050 VIEW AB Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Device User Guide — 9S12C128DGV1/D V01.05 0.20 4X 28 TIPS VIEW AB 0.10 112X SEATING PLANE 0.25 GAGE PLANE Dimensions (case no.
  • Page 134 Device User Guide — 9S12C128DGV1/D V01.05...
  • Page 135 Device User Guide — 9S12C128DGV1/D V01.05 Device User Guide End Sheet...
  • Page 136 Device User Guide — 9S12C128DGV1/D V01.05 FINAL PAGE OF PAGES...

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