Pci Interface; P2 I/O; Programming Model; Processor Memory Maps - Motorola MVME2300 Series Programmer's Reference Manual

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PCI interface

MVME2300 and MVME2300SC boards are equipped with two IEEE
1386.1 PCI Mezzanine Card (PMC) slots. The PMC slots are 64-bit
capable and support both front and rear I/O.

P2 I/O

Certain pins of each PMC slot connector are routed to VME backplane
connector P2 for use in rear I/O configurations.
On MVME2300 boards, pins 1-64 of PMC slot 1 connector J14 are routed
to rows C and A of the 5-row DIN P2 connector. Pins 1-46 of PMC slot 2
connector J24 are routed to rows D and Z of connector P2.
On MVME2300SC boards, pins 1-32 of PMC slot 1 connector J14 are
routed to rows C and A of the 3-row DIN P2 connector. Pins 1-32 of PMC
slot 2 connector J24 (as with J14) are routed to rows C and A of connector
P2.
Additional PCI expansion is supported with a 114-pin Mictor connector.
This connection allows stacking of one or two PMCspan dual-PMC carrier
boards, to increase the I/O capability. Each PMCspan board requires an
additional VME slot.

Programming Model

The following sections describe the memory maps for the MVME2300
series boards.

Processor Memory Maps

The Processor memory map is controlled by the Raven ASIC and the
Falcon chip set. The Raven ASIC and the Falcon chip set have flexible
programming Map Decoder registers to customize the system for many
different applications.
http://www.motorola.com/computer/literature
Programming Model
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