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Falcon ECC Memory Controller Chip Set
ROM B Base/Size Register
Address
Bit
3
Name
Operation
Reset
3-48
ROM B BASE
READ/WRITE
$FF4 PL
ROM B BASE
These control bits define the base address for ROM/Flash
Block B. ROM B BASE bits 0-11 correspond to
PowerPC 60x address bits 0-11 respectively. For larger
ROM/Flash sizes, the lower significant bits of ROM B
BASE are ignored. This means that the block's base
address will always appear at an even multiple of its size.
ROM B BASE is initialized to $FF4 at power-up or local
bus reset.
Note that in addition to the programmed address, the first
1Mbyte of Block B also appears at $FFF00000 -
$FFFFFFFF if the rom_b_rv bit is set.
Also note that the combination of ROM_B_BASE and
rom_b_siz should never be programmed such that
ROM/Flash block B responds at the same address as the
CSR, DRAM, External Register set, or any other slave on
the PowerPC bus.
rom_b_64
rom_b_64 indicates the width of the ROM/Flash
device(s) being used for block B. When rom_b_64 is
cleared, block B is 16 bits wide, where each Falcon
interfaces to 8 bits. When rom_b_64 is set, block B is 64
bits wide, where each Falcon interfaces to 32 bits.
$FEF80058
READ ZERO
X
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