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Raven PCI Bridge ASIC
Interrupt Acknowledge Registers
2
Offset
Bit
3
1
Name
Operation
Reset
End-of-Interrupt Registers
Offset
Bit
3
1
Name
Operation
Reset
2-86
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
R
$00
On PowerPC-based systems, Interrupt Acknowledge is implemented as a
read request to a memory-mapped Interrupt Acknowledge register.
Reading the Interrupt Acknowledge register returns the interrupt vector
corresponding to the highest-priority pending interrupt. Reading this
register also has the following side effects.
The associated bit in the Interrupt Pending register is cleared.
Reading this register will update the In-Service register.
Reading this register without a pending interrupt will return a value of $FF
hexadecimal.
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
R
$00
EOI
End Of Interrupt. There is one EOI register per
processor. EOI code values other than 0 are currently
undefined. Data values written to this register are ignored;
zero is assumed. Writing to this register signals the end of
Processor 0 $200A0
Processor 1 $210A0
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
R
$00
$00
Processor 0 $200B0
Processor 1 $210B0
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
R
$00
$00
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1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
VECTOR
R
R
$FF
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
R
$0
EOI
W
$0
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