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Dispatch register has two addresses. These registers are considered to be
per-processor registers and there is one address per processor. Reading
these registers returns zeros.
P1
P0
Interrupt Task Priority Registers
Offset
Bit
3
3
2
2
1
0
9
8
Name
Operation
R
Reset
$00
There is one Task Priority register per processor. Priority levels from 0
(lowest) to 15 (highest) are supported. Setting the Task Priority register to
15 masks all interrupts to this processor. Hardware will set the task register
to $F when it is reset, or when the Init bit associated with this processor is
written to a 1.
http://www.motorola.com/computer/literature
Processor 1. The interrupt is directed to processor 1.
Processor 0. The interrupt is directed to processor 0.
Processor 0 $20080
Processor 1 $21080
2
2
2
2
2
2
2
2
1
7
6
5
4
3
2
1
0
9
INTERRUPT TASK PRIORITY
R
$00
Raven Interrupt Controller
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$00
TP
R
R/W
$0
$F
2-85
2
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