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Raven PCI Bridge ASIC
2
MPC Error Address Register
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
2-40
SERR
PCI System Error. This bit is set when the PCI SERR
pin is asserted. The bit may be cleared by writing it to a 1;
writing it to a 0 has no effect. When the SERRM bit in the
MEREN register is set, the assertion of this bit will assert
MCHK to the master designated by the DFLT bit in the
MERAT register. When the SERRI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.
SMA
PCI Master Signalled Master Abort. This bit is set
when the PCI master signals master abort to terminate a
PCI transaction. The bit may be cleared by writing it to a
1; writing it to a 0 has no effect. When the SMAM bit in
the MEREN register is set, the assertion of this bit will
assert MCHK to the master designated by the MID field
in the MERAT register. When the SMAI bit in the
MEREN register is set, the assertion of this bit will assert
an interrupt through the MPIC interrupt controller.
RTA
PCI Master Received Target Abort. This bit is set when
the PCI master receives target abort to terminate a PCI
transaction. The bit may be cleared by writing it to a 1;
writing it to a 0 has no effect. When the RTAM bit in the
MEREN register is set, the assertion of this bit will assert
MCHK to the master designated by the MID field in the
MERAT register. When the RTAI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.
1
1
1
0
1
2
$FEFF0028
1
1
1
1
1
1
1
2
2
3
4
5
6
7
8
9
0
1
MERAD
R
$00000000
Computer Group Literature Center Web Site
2
2
2
2
2
2
2
2
3
2
3
4
5
6
7
8
9
0
3
1
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