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Perspective from the MPC bus in Little-Endian mode
Offset
$CFC
Bit (DL)
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
The register fields are defined as follows:
REG
FUN
DEV
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$CFD
1
1
1
0
1
2
CONFIG_ADDRESS
BUS
R
R/W
$00
$00
Register Number.
Configuration Cycles: Identifies a target double word within a
target's configuration space. This field is copied to the PCI AD bus
during the address phase of a Configuration cycle.
Special Cycles: This field must be written with all 0s.
Function Number.
Configuration Cycles: Identifies a function number within a
target's configuration space. This field is copied to the PCI AD bus
during the address phase of a Configuration cycle.
Special Cycles: This field must be written with all 1s.
Device Number.
Configuration Cycles: Identifies a target's physical PCI device
number. Refer to the section on
Cycles
for a description of how this field is encoded.
Special Cycles: This field must be written with all 1s.
$CFE
1
1
1
1
1
1
1
2
2
2
3
4
5
6
7
8
9
0
1
2
DEV
FUN
R/W
R/W
$00
$0
Generating PCI Configuration
Raven Registers
$CFF
2
2
2
2
2
2
2
3
3
3
4
5
6
7
8
9
0
1
REG
R/W
$00
2-57
2
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