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Raven PCI Bridge ASIC
CONFIG_ADDRESS Register
2
Offset
Bit
Name
Operation
Reset
Offset
Bit (DH)
Name
Operation
Reset
2-56
The description of the CONFIG_ADDRESS register is presented in three
perspectives: from the PCI bus, from the MPC bus in big-endian mode, and
from the MPC bus in little-endian mode. Note that the view from the PCI
bus is purely conceptual, since there is no way to access the
CONFIG_ADDRESS register from the PCI bus.
Conceptual perspective from the PCI bus
$CFB
3
3
2
2
2
2
2
2
2
2
1
0
9
8
7
6
5
4
3
2
R
$00
Perspective from the MPC bus in Big-Endian mode
$CF8
0 1 2 3 4 5 6 7 8 9
REG
DEV
R/W
R/W
$00
$CFA
$CF9
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
CONFIG_ADDRESS
BUS
DEV
R/W
R/W
$00
$00
$CF9
$CFA
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
CONFIG_ADDRESS
FUN
R/W
$00
$0
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$CF8
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
REG
FUN
R/W
R/W
$0
$00
$CFB
1
2
2
2
2
2
2
2
2
9
0
1
2
3
4
5
6
7
BUS
R/W
R
$00
$00
2
2
3
3
8
9
0
1
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