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Falcon ECC Memory Controller Chip Set
3
Figure 3-4. Data Path for Reads from the Falcon Internal CSRs
3-22
Accesses to the CSR are mapped differently depending on whether they
are reads or writes. For reads, CSR data read on the upper half of the data
bus comes from the upper Falcon while CSR data read on the lower half of
the data bus comes from the lower Falcon. (See
MPC60x Master
CSR
Upper FALCON
For writes, internal register or test SRAM data written on the upper half of
the data bus goes to the upper Falcon and is automatically copied by
hardware to the lower Falcon. Internal register or test SRAM data written
on the lower half of the data bus does not go to either Falcon in the pair,
but the access is terminated normally with TA_. (See
Figure
CSR
Lower FALCON
1903 9609
Figure
Computer Group Literature Center Web Site
3-4.)
3-5.)
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