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Raven PCI Bridge ASIC
2
Timer Destination Registers
Offset
Bit
3
1
Name
Operation
Reset
2-80
PRIOR
Interrupt Priority. Priority 0 is the lowest and 15 is the
highest. Note that a priority level of 0 will not enable
interrupts.
VECTOR Interrupt Vector. This vector is returned when the
Interrupt Acknowledge register is examined upon
acknowledgment of the interrupt associated with this
vector.
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
R
$00
This register indicates the destinations for this timer's interrupts. Timer
interrupts operate in the Directed delivery interrupt mode. This register
may specify multiple destinations (multicast delivery).
P1
PROCESSOR 1. The interrupt is directed to processor 1.
P0
PROCESSOR 0. The interrupt is directed to processor 0.
Timer 0 - $01130
Timer 1 - $01170
Timer 2 - $011B0
Timer 3 - $011F0
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
TIMER DESTINATION
R
$00
$00
Computer Group Literature Center Web Site
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
R
$00
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