Table of Contents
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status bit, definition of
symbols, use of
syndrome codes, ECC (Falcon chip set)
System Configuration register (SYSCR)
System External Cache Control register (SX-
CCR)
T
Timer registers (Raven MPIC)
Base Count registers
Current Count registers
Destination registers
Frequency register
Vector/Priority registers
timing (DRAM access) 3-7, 3-8,
timing (ROM/Flash access)
transaction ordering (Raven PCI Bridge
ASIC)
triple- (or greater) bit errors (Falcon chip set)
3-13
true, use of
xxiii
U
UCSR access mechanisms
underscore (_), meaning of
Universe (VMEbus to PCI) interface chip
architectural diagram
as PCI master
as PCI slave
as VMEbus master
as VMEbus slave
byte ordering
chip problems after PCI reset 4-14,
Control and Status registers (UCSR)
interrupter and interrupt handler
I
PCI Register values for CHRP memory
map
N
PCI register values for PREP memory
D
map
E
PCI register values for VMEbus slave
X
map
register map
IN-8
xxiii
xxii
1-29
2-78
2-78
2-80
2-77
2-79
3-9
3-10
2-29
4-9
xxiii
4-4
4-6
4-5
4-5
4-4
5-14
4-6
1-15
1-19
1-23
4-9
upper/lower chip status bit (Falcon chip set)
3-32
3-57
V
1-25
Vendor ID/Device ID registers 2-32,
Vendor Identification register (RavenMPIC)
2-75
Vendor/Device register (Falcon chip set)
3-30
VME
Geographical
(VGAR)
VME registers
VMEbus
interface
4-4
interrupt handling (Universe ASIC)
mapping
1-20
master map
slave map 1-21,
Universe ASIC and
W
W83C553 PIB registers
Watchdog Timer registers
word, definition of
write posting (Raven PCI Bridge ASIC)
4-1
writing to control registers (Falcon chip set)
3-53
Z
Z8536 emulation (CIO port pins)
5-9
4-8
Computer Group Literature Center Web Site
Index
2-49
Address
register
1-43
1-37
1-20
1-24
4-1
1-31
1-32
xxiii
1-44
4-7
2-17
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