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Programming Details
Table 5-2. RavenMPIC Interrupt Assignments (Continued)
MPIC
Edge/
IRQ
Level
IRQ14
Level
IRQ15
N/A
5
8259 Interrupts
5-4
Polarity
Low
LM/SIG Interrupt 1
N/A
Not used
Notes
1. Interrupt from the PCI/ISA Bridge.
2. Interrupt from the Falcon chip set for a single and/or double bit
memory error.
3. The mapping of interrupt sources from the VMEbus and Universe
internal interrupt sources is programmable via the Local Interrupt
Map 0 Register and the Local Interrupt Map 1 Register in the
Universe ASIC.
4. These interrupts also appear at the PIB for backward compatibility
with older MVME1600 and PM603/4 modules.
There are 15 interrupt requests supported by the PIB. These 15 interrupts
are ISA-type interrupts that are functionally equivalent to two 82C59
interrupt controllers. Except for IRQ0, IRQ1, IRQ2, IRQ8_, and IRQ13,
each of the interrupt lines can be configured for either edge-sensitive mode
or level-sensitive mode by programming the appropriate ELCR registers
in the PIB.
There is also support for four PCI interrupts, PIRQ3_-PIRQ0_. The PIB
has four PIRQ Route Control registers to allow each of the PCI interrupt
lines to be routed to any of eleven ISA interrupt lines (IRQ0, IRQ1, IRQ2,
IRQ8_, and IRQ13 are reserved for ISA system interrupts). Since PCI
interrupts are defined as level-sensitive, software must program the
selected IRQ(s) for level-sensitive mode. Note that more than one PCI
Interrupt Source
Computer Group Literature Center Web Site
Notes
4
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