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reading internal CSRs
single-beat reads/writes
software considerations
writing to internal CSRs
Falcon-controlled system registers
false, definition of
xxiii
fast refresh control bit (Falcon chip set)
Feature Reporting register (RavenMPIC)
2-73
features
Falcon ECC Memory Controller chip set
3-1
MVME2300 series boards
Raven PCI Bridge ASIC
Universe ASIC 4-1,
Flash (see ROM/Flash interface)
functional description
Falcon ECC Memory Controller chip set
3-5
Raven PCI Bridge ASIC
Universe ASIC
4-3
G
General Control/Status and Feature registers
2-33
General-Purpose registers
general-purpose software-readable header
(J10/J17)
1-32
generating PCI cycles (Raven PCI Bridge
ASIC)
2-21
Global Configuration register (RavenMPIC)
2-74
H
half-word, definition of
xxiii
headers
J10/J17 (general-purpose software-read-
able header)
hexadecimal character, symbol for
hints for programming
5-1
http://www.motorola.com/computer/literature
3-22
3-6
3-53
3-23
1-24
3-32
1-2
2-1
4-2
3-14
2-4
2-47
1-32
xxii
I
I/O Base register
2-52
initializing ROM/Flash
5-15
In-Service register (ISR)
Interprocessor Interrupt Dispatch registers
(Raven MPIC)
interprocessor interrupts
Interrupt Acknowledge registers (Raven
MPIC) 2-86,
2-90
interrupt delivery modes (Raven ASIC)
Interrupt Enable control bits (Falcon chip set)
3-38
interrupt handling, MVME2300 boards
Interrupt Pending register (IPR)
Interrupt Request register (IRR)
interrupt router (Raven ASIC)
interrupt selector (IS)
2-66
Interrupt Task Priority registers (Raven-
MPIC)
2-85
interrupter and interrupt handler (Universe
ASIC)
4-6
IPI Vector/Priority registers (Raven MPIC)
2-76
ISA local resource bus
1-31
J
jumper headers
J10/J17 (general-purpose software-read-
able header)
L
Large Scale Integration (LSI)
little-endian byte ordering xxiii,
LM/SIG Control register
LM/SIG Status register
1-39
Location Monitor
Lower Base Address register
Upper Base Address register
M
manual terminology
xxiii
manufacturers' documents
2-67
2-84
2-89
2-64
5-2
2-66
2-67
2-67
1-32
1-1
5-12
1-38
1-41
1-41
A-2
IN-3
I
N
D
E
X
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