Table 3-2. Powerpc 60 X Bus To Dram Access Timing - 70Ns Page Devices - Motorola MVME2300 Series Programmer's Reference Manual

Table 3-2. PowerPC 60 x Bus to DRAM Access Timing — 70ns Page Devices
Access Type
4-Beat Read after Idle (Quad-
word aligned)
4-Beat Read after Idle (Quad-
word misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write
Notes
1. These numbers assume that the PowerPC 60x bus master is doing
2. In some cases, the numbers shown are averages and specific
http://www.motorola.com/computer/literature
Clock Periods Required For:
1st
Beat
10
10
1
9/3
1
7/2
4
1
10/6
10
1
11/7
4
1
15/11
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also, the two numbers shown in the 1st Beat
column are for page miss/page hit.
instances may be longer or shorter.
Functional Description
2nd 3rd
Beat Beat
1 3
4 1
1 3
4 1
1 1
1 1
- -
- -
-
-
- -
Total
4th
Clocks
Beat
1 15
1 16
1 14/8
1 13/8
7
1
1 13/9
10
-
11/7
-
4
-
- 15/11
3-7
3