System External Cache Control Register (Sxccr) - Motorola MVME2300 Series Programmer's Reference Manual

L2_PLL[0:3]
FLSHP[0:2]

System External Cache Control Register (SXCCR)

The MVME2300 and MVME2300SC boards do not implement this
register. Writes to this register location ($FEF88000) will have no system
effects. Reads from this register location will return undefined data.
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L2 Core Frequency to L2 Frequency divider. This field is
encoded as follows:
0B0110 to 0B1111
Bank A Flash memory size. This field is encoded as
follows:
Flash Size FLSHP0_
1MB 0
2MB 0
4MB 0
8MB 0
16MB 1
32MB 1
64MB 1
No Flash 1
Programming Model
PLL Value]
0B0000
0B0001
0B0010
0B0011
0B0100
0B0101
FLSHP1_
0
0
1
1
0
0
1
1
Size
Disable
1
1.5
2
2.5
3
Reserved
FLSHP2_
0
1
0
1
0
1
0
1
1-29
1