Device Memory Map; Table 1-1 Device Register Map Overview - Motorola MC9S12C-Family User Manual

Device User Guide — 9S12C128DGV1/D V01.05

1.5 Device Memory Map

Table 1-1 shows the device register map of the MC9S12C-Family after reset. The following figures
(Figure 1-2, Figure 1-2, Figure 1-3 and Figure 1-4) illustrate the full device memory map with flash
and RAM.
Address
$000 - $017
$018
$019
$01A - $01B
$01C - $01F
$020 - $02F
$030 - $033
$034 - $03F
$040 - $06F
$070 - $07F
$080 - $09F
$0A0 - $0C7
$0C8 - $0CF
$0D0 - $0D7
$0D8 - $0DF
$0E0 - $0FF
$100 - $10F
$110 - $13F
$140 - $17F
$180 - $23F
$240 - $27F
$280 - $3FF
NOTES:
1. External memory paging is not supported on this device (6.1.1 PPAGE).
2. Not available on MC9S12GC-Family Devices
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Table 1-1 Device Register Map Overview

CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Voltage Regulator (VREG)
Device ID register
CORE (MEMSIZ, IRQ, HPRIO)
CORE (DBG)
1
CORE (PPAGE )
Clock and Reset Generator (CRG)
Standard Timer Module16-bit 8-channels (TIM)
Reserved
Analog to Digital Convert (ATD)
Reserved
Serial Communications Interface (SCI)
Reserved
Serial Peripheral Interface (SPI)
Pulse Width Modulator 8-bit 6 channels (PWM)
Flash Control Register
Reserved
Motorola Scalable CAN (MSCAN)
Reserved
Port Integration Module (PIM)
Reserved
Module
2
Size
24
1
1
2
4
16
4
12
48
16
32
40
8
8
8
32
16
48
64
192
64
384