Ms430 Memory Block Diagram - DEC 4000 AXP Service Manual

Figure 6–6 MS430 Memory Block Diagram
Serial Control Bus
Serial Control Bus
EEPROM
BANK 3 (256 Data + 24 EDC Bits)
BANK 2 (256 Data + 24 EDC Bits)
BANK 2 (256 Data + 24 EDC Bits)
BANK 0 (256 Data + 24 EDC Bits)
DRAM
Data
128
Address and
Data
Control Drivers
+
12 EDC
Bits
Even Slice
Memory Controller
CBUS
CAD
<31:0>
&
<95:64>
System Bus
6–12 System Configuration and Setup
To memory modules,I/O module,
power supply and operator control panel
THIS FIGURE IS SCALED AT 85/100
DRAM Addr & CD
Address and
Control Drivers
System Bus Interface (SBI)
Memory Controller
Clock
Buffers
<127:96>
To memory module, I/O module, and CPU modules
DRAM
Data
128
Data
+
12 EDC
Bits
Odd Slice
CBUS
CAD
<63:32>
&
LJ-02055-TI0