DEC 4000 AXP Service Manual page 147

CPU Features
Each CPU has the following features:
• DECchip 21064 processor chip (approximately 100 MIPS, 20 MFLOPS)
• 1-MB direct-mapping backup cache (physical write-back cache, 32-byte block
size)
• Interface to system bus (128 bits wide)
• System bus arbiter
• System bus clock generator/distributor
Although both CPUs in a dual-processor system have system bus clock
and master bus arbitration circuitry, they are enabled on CPU 0.
• Serial control bus controller for communications with other components of the
system
DECchip 21064 Features
The DECchip 21064 microprocessor is a CMOS-4 superscalar, superpipelined
implementation of the Alpha AXP architecture.
The microprocessor has the following features:
• All instructions are 32 bits long and have a regular instruction format
• Floating-point unit, supports Digital and IEEE floating-point data types
• 32 integer registers, 64 bits wide
• 32 floating-point registers, 64 bits wide
• On-chip 8-KB, direct-mapping, write-through physical data cache
• On-chip 8-KB, direct-mapping, read-only virtual instruction cache
• On-chip 8-entry I-stream translation buffer
• On-chip 32-entry D-stream translation buffer
• Serial ROM interface for booting and diagnostics
• Clock generator
• Packaged in a 431-pin PGA package.
Note
System Configuration and Setup 6–9